diff --git a/chisel b/chisel
index 1f290140..32aad63f 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 1f290140295171bef466917f43a8c7ccb1d8797d
+Subproject commit 32aad63fa38d140797584459e4e8f3f90f11adae
diff --git a/emulator/Makefile b/emulator/Makefile
index 90c21f8b..b7cf6e22 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -12,8 +12,8 @@ CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc -I../dramsim2
 OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
 DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
 
-CHISEL_ARGS := $(MODEL) --backend c --targetDir ../emulator/generated-src
-CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd
+CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir ../emulator/generated-src
+CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
 
 generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
 	cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
diff --git a/riscv-rocket b/riscv-rocket
index d568979c..c89f0033 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit d568979ccbee880cf38a4737f2babc4f9812dfa3
+Subproject commit c89f0033f4834b5b90efd78749f82b0c4e7c6bc6
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 1c14934f..3ac005c5 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -207,8 +207,8 @@ class Top extends Component {
     val hl = uncore.io.htif(i)
     val tl = uncore.io.tiles(i)
 
-    val ic = ICacheConfig(128, 2, co)
-    val dc = DCacheConfig(128, 4, co,
+    val ic = ICacheConfig(128, 2, co, ntlb = 8, nbtb = 16)
+    val dc = DCacheConfig(128, 4, co, ntlb = 8,
                           nmshr = 2, nrpq = 16, nsdq = 17)
     val rc = RocketConfiguration(NTILES, co, ic, dc,
                                  fpu = true, vec = true)