riscv/rocket-chip
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standardize IO naming convention

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This commit is contained in:
Henry Cook
2013-01-07 13:38:59 -08:00
parent 261e14f831
commit e1225c5114
14 changed files with 82 additions and 71 deletions
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7
rocket/src/main/scala/tile.scala
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@ -6,7 +6,7 @@ import Constants._
import uncore._
import Util._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: CoherencePolicyWithUncached,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
fastLoadWord: Boolean = true,
@ -25,11 +25,12 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
{
val memPorts = 2 + confIn.vec
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
implicit val lnConf = confIn.lnConf
implicit val conf = confIn.copy(dcache = dcConf)
val io = new Bundle {
val tilelink = new ioTileLink
val host = new ioHTIF(conf.ntiles)
val tilelink = new TileLinkIO
val host = new HTIFIO(lnConf.nTiles)
}
val core = new Core