From e1225c5114c697d6e84533cc84a9607dd8b77b24 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 7 Jan 2013 13:38:59 -0800 Subject: [PATCH] standardize IO naming convention --- rocket/src/main/scala/arbiter.scala | 10 +++++----- rocket/src/main/scala/core.scala | 12 ++++++------ rocket/src/main/scala/ctrl.scala | 14 +++++++------- rocket/src/main/scala/ctrl_vec.scala | 12 ++++++------ rocket/src/main/scala/dpath.scala | 16 ++++++++-------- rocket/src/main/scala/dpath_util.scala | 6 +++--- rocket/src/main/scala/dpath_vec.scala | 10 +++++----- rocket/src/main/scala/fpu.scala | 8 ++++---- rocket/src/main/scala/htif.scala | 26 ++++++++++++++++++-------- rocket/src/main/scala/icache.scala | 10 +++++----- rocket/src/main/scala/nbdcache.scala | 10 +++++----- rocket/src/main/scala/ptw.scala | 10 +++++----- rocket/src/main/scala/tile.scala | 7 ++++--- rocket/src/main/scala/tlb.scala | 2 +- 14 files changed, 82 insertions(+), 71 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 119362ee..c748141e 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -8,8 +8,8 @@ import uncore._ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val requestor = Vec(n) { new ioHellaCache()(conf.dcache) }.flip - val mem = new ioHellaCache()(conf.dcache) + val requestor = Vec(n) { new HellaCacheIO()(conf.dcache) }.flip + val mem = new HellaCacheIO()(conf.dcache) } val r_valid = io.requestor.map(r => Reg(r.req.valid)) @@ -48,7 +48,7 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp } } -class ioUncachedRequestor extends Bundle { +class UncachedRequestorIO extends Bundle { val xact_init = (new FIFOIO) { new TransactionInit } val xact_abort = (new FIFOIO) { new TransactionAbort }.flip val xact_rep = (new FIFOIO) { new TransactionReply }.flip @@ -57,8 +57,8 @@ class ioUncachedRequestor extends Bundle { class MemArbiter(n: Int) extends Component { val io = new Bundle { - val mem = new ioUncachedRequestor - val requestor = Vec(n) { new ioUncachedRequestor }.flip + val mem = new UncachedRequestorIO + val requestor = Vec(n) { new UncachedRequestorIO }.flip } var xi_bits = new TransactionInit diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index 2c161514..2c27e514 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -6,17 +6,17 @@ import Constants._ import hwacha._ import Util._ -class ioRocket(implicit conf: RocketConfiguration) extends Bundle +class RocketIO(implicit conf: RocketConfiguration) extends Bundle { - val host = new ioHTIF(conf.ntiles) - val imem = new IOCPUFrontend()(conf.icache) - val vimem = new IOCPUFrontend()(conf.icache) - val dmem = new ioHellaCache()(conf.dcache) + val host = new HTIFIO(conf.lnConf.nTiles) + val imem = new CPUFrontendIO()(conf.icache) + val vimem = new CPUFrontendIO()(conf.icache) + val dmem = new HellaCacheIO()(conf.dcache) } class Core(implicit conf: RocketConfiguration) extends Component { - val io = new ioRocket + val io = new RocketIO val ctrl = new Control val dpath = new Datapath diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index a5cc132d..c4b23b76 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -7,7 +7,7 @@ import Instructions._ import hwacha._ import ALU._ -class ioCtrlDpath extends Bundle() +class CtrlDpathIO extends Bundle() { // outputs to datapath val sel_pc = UFix(OUTPUT, 3); @@ -318,18 +318,18 @@ object VDecode extends DecodeConstants class Control(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val dpath = new ioCtrlDpath - val imem = new IOCPUFrontend()(conf.icache) - val dmem = new ioHellaCache()(conf.dcache) + val dpath = new CtrlDpathIO + val imem = new CPUFrontendIO()(conf.icache) + val dmem = new HellaCacheIO()(conf.dcache) val dtlb_val = Bool(OUTPUT) val dtlb_kill = Bool(OUTPUT) val dtlb_rdy = Bool(INPUT) val dtlb_miss = Bool(INPUT) val xcpt_dtlb_ld = Bool(INPUT) val xcpt_dtlb_st = Bool(INPUT) - val fpu = new ioCtrlFPU - val vec_dpath = new ioCtrlDpathVec - val vec_iface = new ioCtrlVecInterface + val fpu = new CtrlFPUIO + val vec_dpath = new CtrlDpathVecIO + val vec_iface = new CtrlVecInterfaceIO } var decode_table = XDecode.table diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index fd45b56b..35974ec9 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -6,7 +6,7 @@ import Constants._ import Instructions._ import hwacha.Constants._ -class ioCtrlDpathVec extends Bundle +class CtrlDpathVecIO extends Bundle { val inst = Bits(INPUT, 32) val appvl0 = Bool(INPUT) @@ -18,7 +18,7 @@ class ioCtrlDpathVec extends Bundle val sel_vimm2 = Bits(OUTPUT, 1) } -class ioCtrlVecInterface extends Bundle +class CtrlVecInterfaceIO extends Bundle { val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) @@ -45,10 +45,10 @@ class ioCtrlVecInterface extends Bundle val hold = Bool(OUTPUT) } -class ioCtrlVec extends Bundle +class CtrlVecIO extends Bundle { - val dpath = new ioCtrlDpathVec() - val iface = new ioCtrlVecInterface() + val dpath = new CtrlDpathVecIO + val iface = new CtrlVecInterfaceIO val valid = Bool(INPUT) val s = Bool(INPUT) val sr_ev = Bool(INPUT) @@ -188,7 +188,7 @@ class rocketCtrlVecDecoder extends Component class rocketCtrlVec extends Component { - val io = new ioCtrlVec() + val io = new CtrlVecIO val dec = new rocketCtrlVecDecoder() dec.io.inst := io.dpath.inst diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 93236aaa..e7387a27 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -10,14 +10,14 @@ import hwacha._ class Datapath(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val host = new ioHTIF(conf.ntiles) - val ctrl = new ioCtrlDpath().flip - val dmem = new ioHellaCache()(conf.dcache) - val ptw = new IODatapathPTW().flip - val imem = new IOCPUFrontend()(conf.icache) - val fpu = new ioDpathFPU(); - val vec_ctrl = new ioCtrlDpathVec().flip - val vec_iface = new ioDpathVecInterface() + val host = new HTIFIO(conf.lnConf.nTiles) + val ctrl = (new CtrlDpathIO).flip + val dmem = new HellaCacheIO()(conf.dcache) + val ptw = (new DatapathPTWIO).flip + val imem = new CPUFrontendIO()(conf.icache) + val fpu = new DpathFPUIO + val vec_ctrl = (new CtrlDpathVecIO).flip + val vec_iface = new DpathVecInterfaceIO } // execute definitions diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 067bea05..131ae28c 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -6,7 +6,7 @@ import Constants._ import scala.math._ import Util._ -class ioDpathBTB extends Bundle() +class DpathBTBIO extends Bundle { val current_pc = UFix(INPUT, VADDR_BITS); val hit = Bool(OUTPUT); @@ -21,7 +21,7 @@ class ioDpathBTB extends Bundle() // fully-associative branch target buffer class rocketDpathBTB(entries: Int) extends Component { - val io = new ioDpathBTB(); + val io = new DpathBTBIO val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU @@ -104,7 +104,7 @@ object PCR class PCR(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val host = new ioHTIF(conf.ntiles) + val host = new HTIFIO(conf.lnConf.nTiles) val r = new ioReadPort(conf.nxpr, conf.xprlen) val w = new ioWritePort(conf.nxpr, conf.xprlen) diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 9ef695a2..caceae02 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -6,7 +6,7 @@ import Constants._ import Instructions._ import hwacha.Constants._ -class ioDpathVecInterface extends Bundle +class DpathVecInterfaceIO extends Bundle { val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD)) val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM)) @@ -22,10 +22,10 @@ class ioDpathVecInterface extends Bundle val irq_aux = Bits(INPUT, 64) } -class ioDpathVec extends Bundle +class DpathVecIO extends Bundle { - val ctrl = new ioCtrlDpathVec().flip - val iface = new ioDpathVecInterface() + val ctrl = (new CtrlDpathVecIO).flip + val iface = new DpathVecInterfaceIO val valid = Bool(INPUT) val inst = Bits(INPUT, 32) val vecbank = Bits(INPUT, 8) @@ -41,7 +41,7 @@ class ioDpathVec extends Bundle class rocketDpathVec extends Component { - val io = new ioDpathVec() + val io = new DpathVecIO val nxregs_stage = Mux(io.ctrl.fn === VEC_CFG, io.wdata(5,0), io.inst(15,10)) val nfregs_stage = Mux(io.ctrl.fn === VEC_CFG, io.rs2(5,0), io.inst(21,16)) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index ef6d708c..41fd4cb4 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -152,7 +152,7 @@ class FPUDecoder extends Component io.sigs.wrfsr := wrfsr.toBool } -class ioDpathFPU extends Bundle { +class DpathFPUIO extends Bundle { val inst = Bits(OUTPUT, 32) val fromint_data = Bits(OUTPUT, 64) @@ -165,7 +165,7 @@ class ioDpathFPU extends Bundle { val dmem_resp_data = Bits(OUTPUT, 64) } -class ioCtrlFPU extends Bundle { +class CtrlFPUIO extends Bundle { val valid = Bool(OUTPUT) val nack_mem = Bool(INPUT) val illegal_rm = Bool(INPUT) @@ -456,8 +456,8 @@ class FPUDFMAPipe(val latency: Int) extends Component class FPU(sfma_latency: Int, dfma_latency: Int) extends Component { val io = new Bundle { - val ctrl = new ioCtrlFPU().flip - val dpath = new ioDpathFPU().flip + val ctrl = (new CtrlFPUIO).flip + val dpath = (new DpathFPUIO).flip val sfma = new ioFMA(33) val dfma = new ioFMA(65) } diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index b6f6f3eb..678d3d69 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -6,12 +6,12 @@ import Constants._ import uncore._ import Util._ -class ioDebug extends Bundle +class DebugIO extends Bundle { val error_mode = Bool(OUTPUT); } -class ioHost(val w: Int) extends Bundle +class HostIO(val w: Int) extends Bundle { val clk = Bool(OUTPUT) val clk_edge = Bool(OUTPUT) @@ -26,10 +26,10 @@ class PCRReq extends Bundle val data = Bits(width = 64) } -class ioHTIF(ntiles: Int) extends Bundle +class HTIFIO(ntiles: Int) extends Bundle { val reset = Bool(INPUT) - val debug = new ioDebug + val debug = new DebugIO val pcr_req = (new FIFOIO) { new PCRReq }.flip val pcr_rep = (new FIFOIO) { Bits(width = 64) } val ipi_req = (new FIFOIO) { Bits(width = log2Up(ntiles)) } @@ -39,9 +39,9 @@ class ioHTIF(ntiles: Int) extends Bundle class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent { val io = new Bundle { - val host = new ioHost(w) - val cpu = Vec(conf.ln.nTiles) { new ioHTIF(conf.ln.nTiles).flip } - val mem = new ioTileLink + val host = new HostIO(w) + val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip } + val mem = new TileLinkIO()(conf.ln) } val short_request_bits = 64 @@ -191,7 +191,17 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo io.mem.probe_req.ready := Bool(false) io.mem.probe_rep.valid := Bool(false) io.mem.probe_rep_data.valid := Bool(false) - io.mem.incoherent := Bool(true) + + io.mem.xact_init.header.src := UFix(1) + io.mem.xact_init.header.dst := UFix(0) + io.mem.xact_init_data.header.src := UFix(1) + io.mem.xact_init_data.header.dst := UFix(0) + io.mem.probe_rep.header.src := UFix(1) + io.mem.probe_rep.header.dst := UFix(0) + io.mem.probe_rep_data.header.src := UFix(1) + io.mem.probe_rep_data.header.dst := UFix(0) + io.mem.xact_finish.header.src := UFix(1) + io.mem.xact_finish.header.dst := UFix(0) val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } for (i <- 0 until conf.ln.nTiles) { diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 420377f4..c47c0768 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -43,18 +43,18 @@ class FrontendResp(implicit conf: ICacheConfig) extends Bundle { override def clone = new FrontendResp().asInstanceOf[this.type] } -class IOCPUFrontend(implicit conf: ICacheConfig) extends Bundle { +class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle { val req = new PipeIO()(new FrontendReq) val resp = new FIFOIO()(new FrontendResp).flip - val ptw = new IOTLBPTW().flip + val ptw = new TLBPTWIO().flip val invalidate = Bool(OUTPUT) } class Frontend(implicit c: ICacheConfig) extends Component { val io = new Bundle { - val cpu = new IOCPUFrontend()(c).flip - val mem = new ioUncachedRequestor + val cpu = new CPUFrontendIO()(c).flip + val mem = new UncachedRequestorIO } val btb = new rocketDpathBTB(c.nbtb) @@ -134,7 +134,7 @@ class ICache(implicit c: ICacheConfig) extends Component val datablock = Bits(width = c.databits) }) val invalidate = Bool(INPUT) - val mem = new ioUncachedRequestor + val mem = new UncachedRequestorIO } val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UFix() } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index a9158cfc..0dcbf9dd 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -726,17 +726,17 @@ class HellaCacheExceptions extends Bundle { } // interface between D$ and processor/DTLB -class ioHellaCache(implicit conf: DCacheConfig) extends Bundle { +class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle { val req = (new FIFOIO){ new HellaCacheReq } val resp = (new PipeIO){ new HellaCacheResp }.flip val xcpt = (new HellaCacheExceptions).asInput - val ptw = new IOTLBPTW().flip + val ptw = (new TLBPTWIO).flip } -class HellaCache(implicit conf: DCacheConfig) extends Component { +class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { - val cpu = (new ioHellaCache).flip - val mem = new ioTileLink + val cpu = (new HellaCacheIO).flip + val mem = new TileLinkIO } val indexmsb = conf.untagbits-1 diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index c87a6e5c..7972dc3d 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import Util._ -class IOTLBPTW extends Bundle { +class TLBPTWIO extends Bundle { val req = new FIFOIO()(UFix(width = VPN_BITS)) val resp = new PipeIO()(new Bundle { val error = Bool() @@ -17,7 +17,7 @@ class IOTLBPTW extends Bundle { val invalidate = Bool(INPUT) } -class IODatapathPTW extends Bundle { +class DatapathPTWIO extends Bundle { val ptbr = UFix(INPUT, PADDR_BITS) val invalidate = Bool(INPUT) val status = new Status().asInput @@ -26,9 +26,9 @@ class IODatapathPTW extends Bundle { class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { - val requestor = Vec(n) { new IOTLBPTW }.flip - val mem = new ioHellaCache()(conf.dcache) - val dpath = new IODatapathPTW + val requestor = Vec(n) { new TLBPTWIO }.flip + val mem = new HellaCacheIO()(conf.dcache) + val dpath = new DatapathPTWIO } val levels = 3 diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index f259cf33..1018bde0 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -6,7 +6,7 @@ import Constants._ import uncore._ import Util._ -case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached, +case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: CoherencePolicyWithUncached, icache: ICacheConfig, dcache: DCacheConfig, fpu: Boolean, vec: Boolean, fastLoadWord: Boolean = true, @@ -25,11 +25,12 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon { val memPorts = 2 + confIn.vec implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen) + implicit val lnConf = confIn.lnConf implicit val conf = confIn.copy(dcache = dcConf) val io = new Bundle { - val tilelink = new ioTileLink - val host = new ioHTIF(conf.ntiles) + val tilelink = new TileLinkIO + val host = new HTIFIO(lnConf.nTiles) } val core = new Core diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 101742d3..33c4377d 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -91,7 +91,7 @@ class TLB(entries: Int) extends Component val io = new Bundle { val req = new FIFOIO()(new TLBReq).flip val resp = new TLBResp(entries) - val ptw = new IOTLBPTW + val ptw = new TLBPTWIO } val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) { UFix() }