riscv/rocket-chip
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standardize IO naming convention

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This commit is contained in:
Henry Cook
2013-01-07 13:38:59 -08:00
parent 261e14f831
commit e1225c5114
14 changed files with 82 additions and 71 deletions
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10
rocket/src/main/scala/ptw.scala
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@ -5,7 +5,7 @@ import Node._
import Constants._
import Util._
class IOTLBPTW extends Bundle {
class TLBPTWIO extends Bundle {
val req = new FIFOIO()(UFix(width = VPN_BITS))
val resp = new PipeIO()(new Bundle {
val error = Bool()
@ -17,7 +17,7 @@ class IOTLBPTW extends Bundle {
val invalidate = Bool(INPUT)
}
class IODatapathPTW extends Bundle {
class DatapathPTWIO extends Bundle {
val ptbr = UFix(INPUT, PADDR_BITS)
val invalidate = Bool(INPUT)
val status = new Status().asInput
@ -26,9 +26,9 @@ class IODatapathPTW extends Bundle {
class PTW(n: Int)(implicit conf: RocketConfiguration) extends Component
{
val io = new Bundle {
val requestor = Vec(n) { new IOTLBPTW }.flip
val mem = new ioHellaCache()(conf.dcache)
val dpath = new IODatapathPTW
val requestor = Vec(n) { new TLBPTWIO }.flip
val mem = new HellaCacheIO()(conf.dcache)
val dpath = new DatapathPTWIO
}
val levels = 3