riscv/rocket-chip
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standardize IO naming convention

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This commit is contained in:
Henry Cook
2013-01-07 13:38:59 -08:00
parent 261e14f831
commit e1225c5114
14 changed files with 82 additions and 71 deletions
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10
rocket/src/main/scala/nbdcache.scala
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@ -726,17 +726,17 @@ class HellaCacheExceptions extends Bundle {
}
// interface between D$ and processor/DTLB
class ioHellaCache(implicit conf: DCacheConfig) extends Bundle {
class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
val req = (new FIFOIO){ new HellaCacheReq }
val resp = (new PipeIO){ new HellaCacheResp }.flip
val xcpt = (new HellaCacheExceptions).asInput
val ptw = new IOTLBPTW().flip
val ptw = (new TLBPTWIO).flip
}
class HellaCache(implicit conf: DCacheConfig) extends Component {
class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
val io = new Bundle {
val cpu = (new ioHellaCache).flip
val mem = new ioTileLink
val cpu = (new HellaCacheIO).flip
val mem = new TileLinkIO
}
val indexmsb = conf.untagbits-1