riscv/rocket-chip
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standardize IO naming convention

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This commit is contained in:
Henry Cook
2013-01-07 13:38:59 -08:00
parent 261e14f831
commit e1225c5114
14 changed files with 82 additions and 71 deletions
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14
rocket/src/main/scala/ctrl.scala
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@@ -7,7 +7,7 @@ import Instructions._
import hwacha._
import ALU._
class ioCtrlDpath extends Bundle()
class CtrlDpathIO extends Bundle()
{
// outputs to datapath
val sel_pc = UFix(OUTPUT, 3);
@@ -318,18 +318,18 @@ object VDecode extends DecodeConstants
class Control(implicit conf: RocketConfiguration) extends Component
{
val io = new Bundle {
val dpath = new ioCtrlDpath
val imem = new IOCPUFrontend()(conf.icache)
val dmem = new ioHellaCache()(conf.dcache)
val dpath = new CtrlDpathIO
val imem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)
val dtlb_val = Bool(OUTPUT)
val dtlb_kill = Bool(OUTPUT)
val dtlb_rdy = Bool(INPUT)
val dtlb_miss = Bool(INPUT)
val xcpt_dtlb_ld = Bool(INPUT)
val xcpt_dtlb_st = Bool(INPUT)
val fpu = new ioCtrlFPU
val vec_dpath = new ioCtrlDpathVec
val vec_iface = new ioCtrlVecInterface
val fpu = new CtrlFPUIO
val vec_dpath = new CtrlDpathVecIO
val vec_iface = new CtrlVecInterfaceIO
}
var decode_table = XDecode.table