riscv/rocket-chip
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rocket: flip interrupt rendering so cores are on top

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Wesley W. Terpstra 2017-09-27 12:46:29 -07:00
parent ce01ab2700
commit e07d86aecd
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/RocketCoreplex.scala
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@ -86,7 +86,7 @@ trait HasRocketTiles extends HasSystemBus
wrapper.intOutputNode.foreach { case int => wrapper.intOutputNode.foreach { case int =>
val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency)) val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
rocketIntXing.intnode := int FlipRendering { implicit p => rocketIntXing.intnode := int }
plic.intnode := rocketIntXing.intnode plic.intnode := rocketIntXing.intnode
} }