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Merge pull request #755 from freechipsproject/verilator-plusargs

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Verilator plusargs
This commit is contained in:
Wesley W. Terpstra 2017-06-01 14:34:09 -07:00 committed by GitHub
commit dfb6340927
2 changed files with 3 additions and 5 deletions
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2
emulator/Makefrag-verilator
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@ -21,7 +21,7 @@ $(generated_dir_debug)/%.fir $(generated_dir_debug)/%.d: $(FIRRTL_JAR) $(chisel_
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
# Build and install our own Verilator, to work around versionining issues. # Build and install our own Verilator, to work around versionining issues.
VERILATOR_VERSION=3.884 VERILATOR_VERSION=3.904
VERILATOR_SRCDIR ?= verilator/src/verilator-$(VERILATOR_VERSION) VERILATOR_SRCDIR ?= verilator/src/verilator-$(VERILATOR_VERSION)
VERILATOR_TARGET := $(abspath verilator/install/bin/verilator) VERILATOR_TARGET := $(abspath verilator/install/bin/verilator)
INSTALLED_VERILATOR ?= $(VERILATOR_TARGET) INSTALLED_VERILATOR ?= $(VERILATOR_TARGET)

6
vsrc/plusarg_reader.v
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@ -10,13 +10,11 @@ reg [31:0] myplus;
assign out = myplus; assign out = myplus;
initial begin initial begin
`ifdef SYNTHESIS
myplus = DEFAULT; myplus = DEFAULT;
`ifndef SYNTHESIS `else
`ifndef verilator
// Work-around for https://www.veripool.org/issues/1165
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT; if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
`endif `endif
`endif
end end
endmodule endmodule