From ded246fb9531b3ae6dacfaba6ef7ba791f799862 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 5 Sep 2016 19:45:16 -0700 Subject: [PATCH] tilelink2: relax max transfer size; the real requirement is not exceeding alignment --- src/main/scala/uncore/tilelink2/Fragmenter.scala | 1 - src/main/scala/uncore/tilelink2/Parameters.scala | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 4eb68b0c..f9472f48 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -17,7 +17,6 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten require (isPow2 (maxSize)) require (isPow2 (minSize)) require (minSize < maxSize) - require (maxSize <= TransferSizes.maxAllowed) val fragmentBits = log2Ceil(maxSize / minSize) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 138ff9a5..9a909261 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -50,7 +50,6 @@ case class TransferSizes(min: Int, max: Int) require (min >= 0 && max >= 0) require (max == 0 || isPow2(max)) require (min == 0 || isPow2(min)) - require (max <= TransferSizes.maxAllowed) def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max @@ -70,7 +69,6 @@ case class TransferSizes(min: Int, max: Int) object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) - val maxAllowed = 4096 // transfers larger than 4kB are forbidden in TL2 implicit def asBool(x: TransferSizes) = !x.none } @@ -130,6 +128,11 @@ case class TLManagerParameters( supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max + + // The device had better not support a transfer larger than it's alignment + address.foreach({ case a => + require (a.alignment1 >= maxTransfer-1) + }) } case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)