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Merge pull request #205 from ucb-bar/configurable_memsize

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make memsize configurable
This commit is contained in:
David Biancolin 2016-08-17 18:33:56 -07:00 committed by GitHub
commit de316643d1
2 changed files with 10 additions and 2 deletions
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10
src/main/scala/Configs.scala
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@ -33,7 +33,7 @@ class BasePlatformConfig extends Config (
collapse = true) collapse = true)
lazy val globalAddrMap = { lazy val globalAddrMap = {
val memBase = 0x80000000L val memBase = 0x80000000L
val memSize = 0x10000000L val memSize = site(ExtMemSize)
val intern = AddrMapEntry("int", internalIOAddrMap) val intern = AddrMapEntry("int", internalIOAddrMap)
val extern = AddrMapEntry("ext", externalAddrMap) val extern = AddrMapEntry("ext", externalAddrMap)
@ -44,7 +44,6 @@ class BasePlatformConfig extends Config (
AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))) AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
Dump("MEM_BASE", addrMap("mem").start) Dump("MEM_BASE", addrMap("mem").start)
Dump("MEM_SIZE", memSize)
addrMap addrMap
} }
def makeConfigString() = { def makeConfigString() = {
@ -149,6 +148,7 @@ class BasePlatformConfig extends Config (
case AsyncMemChannels => false case AsyncMemChannels => false
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1) case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case TMemoryChannels => BusType.AXI case TMemoryChannels => BusType.AXI
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
case ConfigString => makeConfigString() case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap case GlobalAddrMap => globalAddrMap
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
@ -182,6 +182,12 @@ class WithNMemoryChannels(n: Int) extends Config(
} }
) )
class WithExtMemSize(n: Long) extends Config(
(pname,site,here) => pname match {
case ExtMemSize => Dump("MEM_SIZE", n)
case _ => throw new CDEMatchError
}
)
class WithAHB extends Config( class WithAHB extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case TMemoryChannels => BusType.AHB case TMemoryChannels => BusType.AHB

2
src/main/scala/RocketChip.scala
View File

@ -43,6 +43,8 @@ case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
case object BuildCoreplex extends Field[Parameters => Coreplex] case object BuildCoreplex extends Field[Parameters => Coreplex]
/** Function for connecting coreplex extra ports to top-level extra ports */ /** Function for connecting coreplex extra ports to top-level extra ports */
case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit] case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
/** Specifies the size of external memory */
case object ExtMemSize extends Field[Long]
/** Utility trait for quick access to some relevant parameters */ /** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters { trait HasTopLevelParameters {