riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use PROJECT rather than MODEL in name of binary and generated src files.

Browse Source
This commit is contained in:
Henry Cook 2016-09-19 13:23:17 -07:00
parent 7b8aa6c839
commit ddcf1b4099
6 changed files with 33 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Makefrag
View File

@ -6,6 +6,10 @@ endif
MODEL ?= TestHarness MODEL ?= TestHarness
PROJECT ?= rocketchip PROJECT ?= rocketchip
CFG_PROJECT ?= $(PROJECT) CFG_PROJECT ?= $(PROJECT)
CONFIG ?= DefaultConfig
# TODO: For now must match rocketchip.Generator
long_name = $(PROJECT).$(CONFIG)
CXX ?= g++ CXX ?= g++
CXXFLAGS := -O1 CXXFLAGS := -O1
@ -50,7 +54,7 @@ bootrom_img = $(base_dir)/bootrom/bootrom.img
#--------------------------------------------------------------------- #---------------------------------------------------------------------
# sed uses -E (instead of -r) for BSD support # sed uses -E (instead of -r) for BSD support
params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm params_file = $(generated_dir)/$(long_name).prm
consts_header = $(generated_dir)/consts.$(CONFIG).h consts_header = $(generated_dir)/consts.$(CONFIG).h
$(consts_header): $(params_file) $(consts_header): $(params_file)
echo "#ifndef __CONST_H__" > $@ echo "#ifndef __CONST_H__" > $@
@ -58,7 +62,7 @@ $(consts_header): $(params_file)
sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@ sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
echo "#endif // __CONST_H__" >> $@ echo "#endif // __CONST_H__" >> $@
params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm params_file_debug = $(generated_dir_debug)/$(long_name).prm
consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h
$(consts_header_debug): $(params_file_debug) $(consts_header_debug): $(params_file_debug)
echo "#ifndef __CONST_H__" > $@ echo "#ifndef __CONST_H__" > $@

5
emulator/Makefile
View File

@ -6,9 +6,6 @@ generated_dir_debug = $(abspath ./generated-src-debug)
sim_dir = . sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output
BACKEND = c
CONFIG ?= DefaultConfig
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
CXXSRCS := emulator SimDTM CXXSRCS := emulator SimDTM
@ -36,7 +33,7 @@ test:
#-------------------------------------------------------------------- #--------------------------------------------------------------------
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(generated_dir)/$(MODEL).$(CONFIG).d -include $(generated_dir)/$(long_name).d
endif endif
$(output_dir)/%.run: $(output_dir)/% $(emu) $(output_dir)/%.run: $(output_dir)/% $(emu)

31
emulator/Makefrag-verilator
View File

@ -1,19 +1,18 @@
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Verilator Generation # Verilator Generation
#-------------------------------------------------------------------- #--------------------------------------------------------------------
firrtl = $(generated_dir)/$(long_name).fir
firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir firrtl_debug = $(generated_dir_debug)/$(long_name).fir
firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir verilog = $(generated_dir)/$(long_name).v
verilog = $(generated_dir)/$(MODEL).$(CONFIG).v verilog_debug = $(generated_dir_debug)/$(long_name).v
verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug) .SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img) $(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
@ -58,19 +57,19 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS))) cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
headers = $(wildcard $(base_dir)/csrc/*.h) headers = $(wildcard $(base_dir)/csrc/*.h)
model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
$(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR) $(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(MODEL).$(CONFIG) mkdir -p $(generated_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)" -CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk $(MAKE) -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR) $(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG) mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)" -CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk $(MAKE) -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk

2
src/main/scala/rocketchip/Generator.scala
View File

@ -77,7 +77,7 @@ trait Generator extends App with HasGeneratorUtilities {
lazy val world = config.toInstance lazy val world = config.toInstance
lazy val params = Parameters.root(world) lazy val params = Parameters.root(world)
lazy val circuit = elaborate(names, params) lazy val circuit = elaborate(names, params)
lazy val longName = names.topModuleClass + "." + names.configs lazy val longName = names.topProject + "." + names.configs
def writeOutputFiles() { def writeOutputFiles() {
TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames))) TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))

3
vsim/Makefile
View File

@ -17,13 +17,12 @@ sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output
BACKEND ?= v BACKEND ?= v
CONFIG ?= DefaultConfig
TB ?= TestDriver TB ?= TestDriver
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag include $(sim_dir)/Makefrag
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(generated_dir)/$(MODEL).$(CONFIG).d -include $(generated_dir)/$(long_name).d
endif endif
include $(base_dir)/vsim/Makefrag-verilog include $(base_dir)/vsim/Makefrag-verilog

18
vsim/Makefrag-verilog
View File

@ -3,27 +3,27 @@
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# If I don't mark these as .SECONDARY then make will delete these internal # If I don't mark these as .SECONDARY then make will delete these internal
# files. # files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir .SECONDARY: $(generated_dir)/$(long_name).fir
firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir firrtl: $(generated_dir)/$(long_name).fir
.PHONY: firrtl .PHONY: firrtl
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.fir $(generated_dir)/%.d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR) $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf $(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen) $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \ cd $(generated_dir) && \
rm -f $@ && \ rm -f $@ && \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \ $(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
mv $@.tmp $@ mv $@.tmp $@
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
echo "\`ifndef CONST_VH" > $@ echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@ echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@ sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@