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refactor tilelink params, compiles but ExampleSmallConfig fails

This commit is contained in:
Henry Cook 2015-10-13 23:44:05 -07:00
parent 9d11b64c75
commit dd5052888d
5 changed files with 53 additions and 56 deletions

2
rocket

@ -1 +1 @@
Subproject commit 3ced30fd6a4686751e2218c5b268c099851dd179
Subproject commit a72afc525edac561fb3cc5d7bb7eb0756e8f83d9

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@ -46,7 +46,7 @@ class DefaultConfig extends ChiselConfig (
log2Up(site(NMemoryChannels)))
case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
case MIFDataBeats => site(TLKey("L2toMC")).dataBits/site(MIFDataBits)
case NastiKey => NastiParameters(
dataBits = site(MIFDataBits),
addrBits = site(PAddrBits),
@ -83,18 +83,18 @@ class DefaultConfig extends ChiselConfig (
//L2 Memory System Params
case NAcquireTransactors => 7
case L2StoreDataQueueDepth => 1
case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
case BuildL2CoherenceManager => (p: Parameters) =>
Module(new L2BroadcastHub()(p.alterPartial({
case InnerTLId => "L1ToL2"
case OuterTLId => "L2ToMC" })))
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC" })))
//Tile Constants
case BuildTiles => {
TestGeneration.addSuites(rv64i.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1ToL2"})))
Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
}
}
case BuildRoCC => None
@ -124,41 +124,33 @@ class DefaultConfig extends ChiselConfig (
case NCustomMRWCSRs => 0
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLNManagers) + site(TLNClients)
case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
case TLDataBeats => 4
case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1
case TLNetworkIsOrderedP2P => false
case TLNManagers => findBy(TLId)
case TLNCachingClients => findBy(TLId)
case TLNCachelessClients => findBy(TLId)
case TLCoherencePolicy => findBy(TLId)
case TLMaxManagerXacts => findBy(TLId)
case TLMaxClientXacts => findBy(TLId)
case TLMaxClientsPerPort => findBy(TLId)
case "L1ToL2" => {
case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels)
case TLNCachingClients => site(NTiles)
case TLNCachelessClients => site(NTiles) + 1
case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
case TLMaxManagerXacts => site(NAcquireTransactors) + 2
case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs),
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + 1,
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
if(site(BuildRoCC).isEmpty) 1
else site(RoCCMaxTaggedMemXacts))
case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
}:PF
case "L2ToMC" => {
case TLNManagers => 1
case TLNCachingClients => site(NBanksPerMemoryChannel)
case TLNCachelessClients => 0
case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel)))
case TLMaxManagerXacts => 1
case TLMaxClientXacts => 1
case TLMaxClientsPerPort => site(NAcquireTransactors) + 2
}:PF
else site(RoCCMaxTaggedMemXacts)),
maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 3,
maxManagerXacts = site(NAcquireTransactors) + 2,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)()
case TLKey("L2toMC") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
addrBits = site(PAddrBits) - site(CacheBlockOffsetBits),
dataBits = site(CacheBlockBytes)*8)()
case NTiles => Knob("NTILES")
case NMemoryChannels => 1
case NBanksPerMemoryChannel => Knob("NBANKS")
@ -204,16 +196,16 @@ class WithL2Cache extends ChiselConfig(
site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
site(NWays)
case NWays => Knob("L2_WAYS")
case RowBits => site(TLDataBits)
case RowBits => site(TLKey(site(TLId))).dataBits
}: PartialFunction[Any,Any]
case NAcquireTransactors => 2
case NSecondaryMisses => 4
case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
case BuildL2CoherenceManager => (p: Parameters) =>
Module(new L2HellaCacheBank()(p.alterPartial({
case CacheName => "L2Bank"
case InnerTLId => "L1ToL2"
case OuterTLId => "L2ToMC"})))
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC"})))
},
knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
)
@ -235,7 +227,7 @@ class WithZscale extends ChiselConfig(
case BuildZscale => {
TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
TestGeneration.addSuites(List(zscaleBmarks))
(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1ToL2"})))
(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
}
case UseZscale => true
case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)

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@ -31,8 +31,8 @@ abstract class RocketChipNetwork(
clientDepths: TileLinkDepths,
managerDepths: TileLinkDepths)
(implicit p: Parameters) extends TLModule()(p) {
val nClients = p(TLNClients)
val nManagers = p(TLNManagers)
val nClients = tlNClients
val nManagers = tlNManagers
val io = new Bundle {
val clients = Vec(new ClientTileLinkIO, nClients).flip
val managers = Vec(new ManagerTileLinkIO, nManagers).flip
@ -95,7 +95,7 @@ class RocketChipTileLinkCrossbar(
(implicit p: Parameters)
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
val n = p(LNEndpoints)
val count = p(TLDataBeats)
val count = tlDataBeats
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))

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@ -30,9 +30,10 @@ case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
case object ExternalIOStart extends Field[BigInt]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters extends HasHtifParameters {
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val nTiles = p(NTiles)
lazy val htifW = w
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
@ -42,6 +43,10 @@ trait HasTopLevelParameters extends HasHtifParameters {
lazy val mifAddrBits = p(MIFAddrBits)
lazy val mifDataBeats = p(MIFDataBeats)
lazy val xLen = p(XLen)
lazy val nSCR = p(HtifKey).nSCR
lazy val scrAddrBits = log2Up(nSCR)
lazy val scrDataBits = 64
lazy val scrDataBytes = scrDataBits / 8
//require(lsb + log2Up(nBanks) < mifAddrBits)
}
@ -55,7 +60,7 @@ class MemBackupCtrlIO extends Bundle {
/** Top-level io for the chip */
class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasTopLevelParameters {
val host = new HostIO
val host = new HostIO(htifW)
val mem_backup_ctrl = new MemBackupCtrlIO
}
@ -98,7 +103,7 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
val io = new MultiChannelTopIO
// Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
@ -130,7 +135,7 @@ class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLeve
*/
class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
val io = new Bundle {
val host = new HostIO
val host = new HostIO(htifW)
val mem = Vec(new NastiIO, nMemChannels)
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
@ -221,7 +226,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
// Create a converter between TileLinkIO and MemIO for each channel
val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
val backendBuffering = TileLinkDepths(0,0,0,0,0)
val addrMap = p(GlobalAddrMap)

2
uncore

@ -1 +1 @@
Subproject commit 69e494348c2b3ea7ff3abed392fcff2fb7cf730c
Subproject commit 3c742a5a91a4405e1de1fe2d8d86ca8e1ed1bfaf