riscv/rocket-chip
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refactor tilelink params, compiles but ExampleSmallConfig fails

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This commit is contained in:
Henry Cook
2015-10-13 23:44:05 -07:00
parent 9d11b64c75
commit dd5052888d
5 changed files with 53 additions and 56 deletions
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6
src/main/scala/Network.scala
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@ -31,8 +31,8 @@ abstract class RocketChipNetwork(
clientDepths: TileLinkDepths,
managerDepths: TileLinkDepths)
(implicit p: Parameters) extends TLModule()(p) {
val nClients = p(TLNClients)
val nManagers = p(TLNManagers)
val nClients = tlNClients
val nManagers = tlNManagers
val io = new Bundle {
val clients = Vec(new ClientTileLinkIO, nClients).flip
val managers = Vec(new ManagerTileLinkIO, nManagers).flip
@ -95,7 +95,7 @@ class RocketChipTileLinkCrossbar(
(implicit p: Parameters)
extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
val n = p(LNEndpoints)
val count = p(TLDataBeats)
val count = tlDataBeats
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))