riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Check PPN LSBs for superpage PTEs

Browse Source 
5a32fe8782
This commit is contained in:
Andrew Waterman 2017-05-05 14:42:14 -07:00 committed by Andrew Waterman
parent 431e726c29
commit dd1546fd69
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/rocket/PTW.scala
View File

@ -95,6 +95,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val tmp = new PTE().fromBits(io.mem.resp.bits.data) val tmp = new PTE().fromBits(io.mem.resp.bits.data)
val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data)) val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data))
res.ppn := tmp.ppn(ppnBits-1, 0) res.ppn := tmp.ppn(ppnBits-1, 0)
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0) { res.v := false }
}
(res, (tmp.ppn >> ppnBits) =/= 0) (res, (tmp.ppn >> ppnBits) =/= 0)
} }
val traverse = pte.table() && !invalid_paddr && count < pgLevels-1 val traverse = pte.table() && !invalid_paddr && count < pgLevels-1