From dd1546fd6903b78e28d062fd165704281bb6a49c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 5 May 2017 14:42:14 -0700 Subject: [PATCH] Check PPN LSBs for superpage PTEs https://github.com/riscv/riscv-isa-manual/commit/5a32fe87820f2f0f7ffab16a4a33906e78e26abb --- src/main/scala/rocket/PTW.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index ae5854b7..d6a5b4fc 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -95,6 +95,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( val tmp = new PTE().fromBits(io.mem.resp.bits.data) val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data)) res.ppn := tmp.ppn(ppnBits-1, 0) + when (tmp.r || tmp.w || tmp.x) { + // for superpage mappings, make sure PPN LSBs are zero + for (i <- 0 until pgLevels-1) + when (count <= i && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0) { res.v := false } + } (res, (tmp.ppn >> ppnBits) =/= 0) } val traverse = pte.table() && !invalid_paddr && count < pgLevels-1