From dcde377303e97e4b7d21bd5e488bc012b5075245 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 20 May 2013 15:22:58 -0700 Subject: [PATCH] Fix DM I$ deadlock BTB predictions were causing infinite miss loops --- rocket/src/main/scala/icache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index e5ad20c9..f4febe9d 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -110,7 +110,7 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) icache.io.invalidate := io.cpu.invalidate icache.io.req.bits.ppn := tlb.io.resp.ppn - icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss + icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss icache.io.resp.ready := !stall && !s1_same_block io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)