new tilelink arbiter types, reduced release xact trackers

uncore/src/consts.scala

@@ -11,7 +11,7 @@ abstract trait CoherenceConfigConstants {
 
 trait UncoreConstants {
   val NGLOBAL_ACQ_XACTS = 8
-  val NGLOBAL_REL_XACTS = 4
+  val NGLOBAL_REL_XACTS = 1
   val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_ACQ_XACTS+NGLOBAL_REL_XACTS)
   val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 
 }

uncore/src/tilelink.scala

@@ -147,12 +147,24 @@ class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends UncachedTil
   override def clone = { new TileLinkIO().asInstanceOf[this.type] }
 }
 
-class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
+/*
+ * TODO: Merge the below classes into children of an abstract class in Chisel 2.0
+abstract class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
+  def acquireClientXactId(in: Acquire, id: Int): Bits
+  def grantClientXactId(in: Grant): Bits
+  def arbIdx(in: Grant): UFix
+}
+*/
+
+class UncachedTileLinkIOArbiterThatAppendsArbiterId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
+  def acquireClientXactId(in: Acquire, id: Int) = Cat(in.client_xact_id, UFix(id, log2Up(n)))
+  def grantClientXactId(in: Grant) = in.client_xact_id >> UFix(log2Up(n))
+  def arbIdx(in: Grant) = in.client_xact_id(log2Up(n)-1,0).toUFix
+
   val io = new Bundle {
     val in = Vec(n) { new UncachedTileLinkIO }.flip
     val out = new UncachedTileLinkIO
   }
-
   def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
   val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
   io.out.acquire <> acq_arb.io.out
@@ -160,7 +172,7 @@ class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: Logi
     arb.data <> req.data
     arb.meta.valid := req.meta.valid
     arb.meta.bits := req.meta.bits
-    arb.meta.bits.payload.client_xact_id := Cat(req.meta.bits.payload.client_xact_id, UFix(id, log2Up(n)))
+    arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
     req.meta.ready := arb.meta.ready
   }}
 
@@ -170,13 +182,85 @@ class UncachedTileLinkIOArbiter(n: Int, co: CoherencePolicy)(implicit conf: Logi
 
   io.out.grant.ready := Bool(false)
   for (i <- 0 until n) {
-    val tag = io.out.grant.bits.payload.client_xact_id
     io.in(i).grant.valid := Bool(false)
-    when (tag(log2Up(n)-1,0) === UFix(i)) {
+    when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
       io.in(i).grant.valid := io.out.grant.valid
       io.out.grant.ready := io.in(i).grant.ready
     }
     io.in(i).grant.bits := io.out.grant.bits
-    io.in(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
+    io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload) 
   }
 }
+
+class UncachedTileLinkIOArbiterThatPassesId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
+  def acquireClientXactId(in: Acquire, id: Int) = in.client_xact_id
+  def grantClientXactId(in: Grant) = in.client_xact_id
+  def arbIdx(in: Grant): UFix = in.client_xact_id
+
+  val io = new Bundle {
+    val in = Vec(n) { new UncachedTileLinkIO }.flip
+    val out = new UncachedTileLinkIO
+  }
+  def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
+  val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
+  io.out.acquire <> acq_arb.io.out
+  io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
+    arb.data <> req.data
+    arb.meta.valid := req.meta.valid
+    arb.meta.bits := req.meta.bits
+    arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
+    req.meta.ready := arb.meta.ready
+  }}
+
+  val grant_ack_arb = (new RRArbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
+  io.out.grant_ack <> grant_ack_arb.io.out
+  grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
+
+  io.out.grant.ready := Bool(false)
+  for (i <- 0 until n) {
+    io.in(i).grant.valid := Bool(false)
+    when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
+      io.in(i).grant.valid := io.out.grant.valid
+      io.out.grant.ready := io.in(i).grant.ready
+    }
+    io.in(i).grant.bits := io.out.grant.bits
+    io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload) 
+  }
+}
+
+class UncachedTileLinkIOArbiterThatUsesNewId(n: Int, co: CoherencePolicy)(implicit conf: LogicalNetworkConfiguration) extends Component {
+  def acquireClientXactId(in: Acquire, id: Int) = UFix(id, log2Up(n))
+  def grantClientXactId(in: Grant) = UFix(0) // DNC 
+  def arbIdx(in: Grant) = in.client_xact_id
+
+  val io = new Bundle {
+    val in = Vec(n) { new UncachedTileLinkIO }.flip
+    val out = new UncachedTileLinkIO
+  }
+  def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
+  val acq_arb = new PairedLockingRRArbiter(n, REFILL_CYCLES, acqHasData _)((new LogicalNetworkIO){new Acquire},(new LogicalNetworkIO){new AcquireData})
+  io.out.acquire <> acq_arb.io.out
+  io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
+    arb.data <> req.data
+    arb.meta.valid := req.meta.valid
+    arb.meta.bits := req.meta.bits
+    arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
+    req.meta.ready := arb.meta.ready
+  }}
+
+  val grant_ack_arb = (new RRArbiter(n)){ (new LogicalNetworkIO){new GrantAck} }
+  io.out.grant_ack <> grant_ack_arb.io.out
+  grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
+
+  io.out.grant.ready := Bool(false)
+  for (i <- 0 until n) {
+    io.in(i).grant.valid := Bool(false)
+    when (arbIdx(io.out.grant.bits.payload) === UFix(i)) {
+      io.in(i).grant.valid := io.out.grant.valid
+      io.out.grant.ready := io.in(i).grant.ready
+    }
+    io.in(i).grant.bits := io.out.grant.bits
+    io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload) 
+  }
+}
+

uncore/src/uncore.scala

@@ -23,7 +23,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
 {
   implicit val lnConf = conf.ln
   val co = conf.co
-  require(conf.ln.nClients < NGLOBAL_REL_XACTS) //TODO: handle in config
+  //require(conf.ln.nClients < NGLOBAL_REL_XACTS) //TODO: handle in config
   val trackerList = (0 until NGLOBAL_REL_XACTS).map(new VoluntaryReleaseTracker(_, bankId)) ++ 
                     (NGLOBAL_REL_XACTS until NGLOBAL_REL_XACTS + NGLOBAL_ACQ_XACTS).map(new AcquireTracker(_, bankId))
   
@@ -60,7 +60,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
   val block_releases = Bool(false)
   val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b}
   //val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
-  val release_idx = Mux(voluntary, release.meta.bits.header.src, release.meta.bits.payload.master_xact_id)
+  val release_idx = Mux(voluntary, UFix(0), release.meta.bits.payload.master_xact_id)
   for( i <- 0 until trackerList.size ) {
     val t = trackerList(i).io.client
     t.release.meta.bits := release.meta.bits 
@@ -83,7 +83,7 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends
   ack.ready := Bool(true)
 
   // Create an arbiter for the one memory port
-  val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size, conf.co)
+  val outer_arb = new UncachedTileLinkIOArbiterThatPassesId(trackerList.size, conf.co)
   outer_arb.io.in zip  trackerList map { case(arb, t) => arb <> t.io.master }
   io.master <> outer_arb.io.out
 }