From daf23b8f79cc08ee7b2e0d9409483084aff7a0e0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 24 Aug 2013 14:42:50 -0700 Subject: [PATCH] Add early out to multiplier --- rocket/src/main/scala/divider.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala index 6c6f0242..bfdfcb2e 100644 --- a/rocket/src/main/scala/divider.scala +++ b/rocket/src/main/scala/divider.scala @@ -54,11 +54,14 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke val accum = mulReg(2*mulw,mulw).toSInt val mpcand = divisor.toSInt val prod = mplier(mulUnroll-1,0) * mpcand + accum - val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt + val eOut = Bool(earlyOut) && count > 0 && + (0 until mulw/mulUnroll).map(i => i > mulw/mulUnroll-1-count || mplier((i+1)*mulUnroll-1,i*mulUnroll) === 0).reduce(_&&_) + val eOutValue = mulReg >> (mulw/mulUnroll-count)(log2Up(mulw/mulUnroll)-1,0)*mulUnroll + val nextMulReg = Mux(eOut, eOutValue, Cat(prod, mplier(mulw-1,mulUnroll))) remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt count := count + 1 - when (count === mulw/mulUnroll-1) { + when (count === mulw/mulUnroll-1 || eOut) { state := s_done when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) { state := s_move_rem