riscv/rocket-chip
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Merge branch 'master' into chisel-v2

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Conflicts:
	src/main/scala/htif.scala
This commit is contained in:
Stephen Twigg 2013-09-05 16:11:53 -07:00
commit d896ccbd43
2 changed files with 10 additions and 6 deletions
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3
rocket/src/main/scala/dpath_util.scala
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@ -117,6 +117,9 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val rdata = Bits(OUTPUT, conf.xprlen) val rdata = Bits(OUTPUT, conf.xprlen)
val wdata = Bits(INPUT, conf.xprlen) val wdata = Bits(INPUT, conf.xprlen)
} }
// there is a fixed constant related to this in PCRReq.addr
require(log2Up(conf.nxpr) == 5)
val status = new Status().asOutput val status = new Status().asOutput
val ptbr = UInt(OUTPUT, PADDR_BITS) val ptbr = UInt(OUTPUT, PADDR_BITS)

13
rocket/src/main/scala/htif.scala
View File

@ -16,7 +16,7 @@ class HostIO(val w: Int) extends Bundle
class PCRReq extends Bundle class PCRReq extends Bundle
{ {
val rw = Bool() val rw = Bool()
val addr = Bits(width = 6) val addr = Bits(width = 5)
val data = Bits(width = 64) val data = Bits(width = 64)
} }
@ -30,7 +30,7 @@ class HTIFIO(ntiles: Int) extends Bundle
val ipi_rep = Decoupled(Bool()).flip val ipi_rep = Decoupled(Bool()).flip
} }
class SCRIO extends Bundle class SCRIO(n: Int) extends Bundle
{ {
val n = 64 val n = 64
val rdata = Vec.fill(n){Bits(INPUT, 64)} val rdata = Vec.fill(n){Bits(INPUT, 64)}
@ -39,7 +39,7 @@ class SCRIO extends Bundle
val wdata = Bits(OUTPUT, 64) val wdata = Bits(OUTPUT, 64)
} }
class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module with ClientCoherenceAgent class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent
{ {
implicit val (ln, co) = (conf.ln, conf.co) implicit val (ln, co) = (conf.ln, conf.co)
val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
@ -47,7 +47,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
val host = new HostIO(w) val host = new HostIO(w)
val cpu = Vec.fill(nTiles){new HTIFIO(nTiles).flip} val cpu = Vec.fill(nTiles){new HTIFIO(nTiles).flip}
val mem = new TileLinkIO val mem = new TileLinkIO
val scr = new SCRIO val scr = new SCRIO(nSCR)
} }
val short_request_bits = 64 val short_request_bits = 64
@ -233,6 +233,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
} }
} }
val scr_addr = addr(log2Up(nSCR)-1, 0)
val scr_rdata = Vec.fill(io.scr.rdata.size){Bits(width = 64)} val scr_rdata = Vec.fill(io.scr.rdata.size){Bits(width = 64)}
for (i <- 0 until scr_rdata.size) for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i) scr_rdata(i) := io.scr.rdata(i)
@ -241,10 +242,10 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
io.scr.wen := false io.scr.wen := false
io.scr.wdata := pcr_wdata io.scr.wdata := pcr_wdata
io.scr.waddr := pcr_addr.toUInt io.scr.waddr := scr_addr.toUInt
when (state === state_pcr_req && pcr_coreid === SInt(-1)) { when (state === state_pcr_req && pcr_coreid === SInt(-1)) {
io.scr.wen := cmd === cmd_writecr io.scr.wen := cmd === cmd_writecr
pcrReadData := scr_rdata(pcr_addr) pcrReadData := scr_rdata(scr_addr)
state := state_tx state := state_tx
} }