From 2ca5127785f66cf18aceff7f58511983e0ca2878 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 15:47:14 -0700 Subject: [PATCH 1/3] parameterize number of SCRs --- rocket/src/main/scala/htif.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 583e90ce..27a79063 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -35,16 +35,15 @@ class HTIFIO(ntiles: Int) extends Bundle val ipi_rep = (new FIFOIO) { Bool() }.flip } -class SCRIO extends Bundle +class SCRIO(n: Int) extends Bundle { - val n = 64 val rdata = Vec(n) { Bits(INPUT, 64) } val wen = Bool(OUTPUT) val waddr = UFix(OUTPUT, log2Up(n)) val wdata = Bits(OUTPUT, 64) } -class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent +class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent { implicit val (ln, co) = (conf.ln, conf.co) val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client @@ -52,7 +51,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component val host = new HostIO(w) val cpu = Vec(nTiles) { new HTIFIO(nTiles).flip } val mem = new TileLinkIO - val scr = new SCRIO + val scr = new SCRIO(nSCR) } val short_request_bits = 64 From 44e92edf923577fd733fd75b95908d1cc3b664cb Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 22:42:51 -0700 Subject: [PATCH 2/3] fix scr parameterization bug --- rocket/src/main/scala/dpath_util.scala | 3 +++ rocket/src/main/scala/htif.scala | 7 ++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 65f377b2..9a861bca 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -113,6 +113,9 @@ class PCR(implicit conf: RocketConfiguration) extends Component val rdata = Bits(OUTPUT, conf.xprlen) val wdata = Bits(INPUT, conf.xprlen) } + + // there is a fixed constant related to this in PCRReq.addr + require(log2Up(conf.nxpr) == 5) val status = new Status().asOutput val ptbr = UFix(OUTPUT, PADDR_BITS) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 27a79063..93e54cc2 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -21,7 +21,7 @@ class HostIO(val w: Int) extends Bundle class PCRReq extends Bundle { val rw = Bool() - val addr = Bits(width = 6) + val addr = Bits(width = 5) val data = Bits(width = 64) } @@ -237,6 +237,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend } } + val scr_addr = addr(log2Up(nSCR)-1, 0) val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)} for (i <- 0 until scr_rdata.size) scr_rdata(i) := io.scr.rdata(i) @@ -245,10 +246,10 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend io.scr.wen := false io.scr.wdata := pcr_wdata - io.scr.waddr := pcr_addr.toUFix + io.scr.waddr := scr_addr.toUFix when (state === state_pcr_req && pcr_coreid === Fix(-1)) { io.scr.wen := cmd === cmd_writecr - pcrReadData := scr_rdata(pcr_addr) + pcrReadData := scr_rdata(scr_addr) state := state_tx } From b9f6e1a7ecbf32fba1943aee34ee92a1be6c863c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 24 Aug 2013 14:40:13 -0700 Subject: [PATCH 3/3] Don't update BTB when garbage was fetched --- rocket/src/main/scala/ctrl.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 682af625..649a8f80 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -655,7 +655,7 @@ class Control(implicit conf: RocketConfiguration) extends Component Mux(!ex_reg_btb_hit, PC_EX, // mispredicted taken branch PC_EX4))))) // mispredicted not taken branch - io.imem.req.bits.mispredict := !take_pc_wb && take_pc_ex + io.imem.req.bits.mispredict := !take_pc_wb && take_pc_ex && !ex_reg_xcpt io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr io.imem.req.valid := take_pc