Merge branch 'master' into chisel-v2

Conflicts:
	src/main/scala/htif.scala

rocket/src/main/scala/dpath_util.scala

@@ -117,6 +117,9 @@ class PCR(implicit conf: RocketConfiguration) extends Module
       val rdata = Bits(OUTPUT, conf.xprlen)
       val wdata = Bits(INPUT, conf.xprlen)
     }
+
+    // there is a fixed constant related to this in PCRReq.addr
+    require(log2Up(conf.nxpr) == 5)
     
     val status = new Status().asOutput
     val ptbr = UInt(OUTPUT, PADDR_BITS)