From d7df7d3109f0bfd4c42020f915349f24ec3cfe4f Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 8 Sep 2016 14:41:08 -0700
Subject: [PATCH] tilelink2: connect Nodes to LazyModules for better error
 messages

---
 .../scala/uncore/tilelink2/LazyModule.scala   | 11 +++++++++--
 src/main/scala/uncore/tilelink2/Nodes.scala   | 19 ++++++++++++++++---
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/LazyModule.scala b/src/main/scala/uncore/tilelink2/LazyModule.scala
index 5937b363..92c6e0eb 100644
--- a/src/main/scala/uncore/tilelink2/LazyModule.scala
+++ b/src/main/scala/uncore/tilelink2/LazyModule.scala
@@ -3,12 +3,13 @@
 package uncore.tilelink2
 
 import Chisel._
-import chisel3.internal.sourceinfo._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
 
 abstract class LazyModule
 {
   protected[tilelink2] var bindings = List[() => Unit]()
   protected[tilelink2] var children = List[LazyModule]()
+  protected[tilelink2] var nodes = List[RootNode]()
   protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo
   protected[tilelink2] val parent = LazyModule.stack.headOption
 
@@ -22,6 +23,12 @@ abstract class LazyModule
     }
   }
 
+  def name = getClass.getName.split('.').last
+  def line = info match {
+    case SourceLine(filename, line, col) => s" ($filename:$line:$col)"
+    case _ => ""
+  }
+
   def module: LazyModuleImp
   implicit val lazyModule = this
 
@@ -55,6 +62,6 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module
   // .module had better not be accessed while LazyModules are still being built!
   require (LazyModule.stack.isEmpty)
 
-  override def desiredName = outer.getClass.getName.split('.').last
+  override def desiredName = outer.name
   outer.instantiate()
 }
diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala
index 0dc8af9e..a2231bbd 100644
--- a/src/main/scala/uncore/tilelink2/Nodes.scala
+++ b/src/main/scala/uncore/tilelink2/Nodes.scala
@@ -19,11 +19,20 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Data]
   def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit
 }
 
+class RootNode
+{
+  // You cannot create a Node outside a LazyModule!
+  require (!LazyModule.stack.isEmpty)
+
+  val lazyModule = LazyModule.stack.head
+  lazyModule.nodes = this :: lazyModule.nodes
+}
+
 class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
   private val oFn: Option[Seq[PO] => PO],
   private val iFn: Option[Seq[PI] => PI],
   private val numPO: Range.Inclusive,
-  private val numPI: Range.Inclusive)
+  private val numPI: Range.Inclusive) extends RootNode
 {
   // At least 0 ports must be supported
   require (!numPO.isEmpty)
@@ -42,8 +51,12 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
   private var oRealized  = false
   private var iRealized = false
 
-  private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
-  private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
+  def name = lazyModule.name + "." + getClass.getName.split('.').last
+  private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
+  private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
+
+  private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
+  private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
   private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
   private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))