riscv/rocket-chip
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more != wire deprecations

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This commit is contained in:
Henry Cook
2018-03-08 12:36:51 -08:00
parent 32592377c6
commit d6e2c1a73f
2 changed files with 2 additions and 2 deletions
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src/main/scala/devices/tilelink/BusBypass.scala
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@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
flight := next_flight
when (next_flight === UInt(0)) { bypass := io.bypass }
val stall = (bypass != io.bypass) && a_first
val stall = (bypass =/= io.bypass) && a_first
out0.a.valid := !stall && in.a.valid && bypass
out1.a.valid := !stall && in.a.valid && !bypass