DebugModule: translate to TL2 with {32,64}-bit XLen width
This commit is contained in:
Megan Wachs
Wesley W. Terpstra
parent
3e08d615f0
commit
d530ef7236
@ -4,8 +4,9 @@ package uncore.devices
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import util._
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import regmapper._
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import uncore.tilelink2._
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import cde.{Parameters, Config, Field}
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// *****************************************
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@ -15,6 +16,7 @@ import cde.{Parameters, Config, Field}
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object DbRegAddrs{
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def DMRAMBASE = UInt(0x0)
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def DMCONTROL = UInt(0x10)
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def DMINFO = UInt(0x11)
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@ -69,7 +71,7 @@ object DsbBusConsts {
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// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
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// The code assumes 64 bytes of Debug RAM.
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def defaultRomContents : Array[Byte] = Array(
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def xlenAnyRomContents : Array[Byte] = Array(
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0x6f, 0x00, 0xc0, 0x04, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
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0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
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0xf3, 0x24, 0x00, 0xf1, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0x43,
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@ -121,10 +123,10 @@ object DsbBusConsts {
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object DsbRegAddrs{
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def CLEARDEBINT = UInt(0x100)
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def SETHALTNOT = UInt(0x10C)
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def SERINFO = UInt(0x110)
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def SERBASE = UInt(0x114)
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def CLEARDEBINT = 0x100
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def SETHALTNOT = 0x10C
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def SERINFO = 0x110
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def SERBASE = 0x114
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// For each serial, there are
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// 3 registers starting here:
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// SERSEND0
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@ -132,9 +134,11 @@ object DsbRegAddrs{
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// SERSTATUS0
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// ...
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// SERSTATUS7
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def SERTX_OFFSET = UInt(0)
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def SERRX_OFFSET = UInt(4)
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def SERSTAT_OFFSET = UInt(8)
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def SERTX_OFFSET = 0
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def SERRX_OFFSET = 4
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def SERSTAT_OFFSET = 8
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def RAMBASE = 0x400
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def ROMBASE = 0x800
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}
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@ -302,6 +306,24 @@ class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p
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val resp = new DecoupledIO(new DebugBusResp).flip()
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}
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trait HasDebugModuleParameters {
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val params : Parameters
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implicit val p = params
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val cfg = p(DMKey)
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}
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/** Debug Module I/O, with the exclusion of the RegisterRouter
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* Access interface.
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*/
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trait DebugModuleBundle extends Bundle with HasDebugModuleParameters {
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val db = new DebugBusIO()(p).flip()
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val debugInterrupts = Vec(cfg.nComponents, Bool()).asOutput
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val ndreset = Bool(OUTPUT)
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val fullreset = Bool(OUTPUT)
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}
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// *****************************************
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// The Module
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//
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@ -313,7 +335,7 @@ class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p
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* DebugModule is a slave to two masters:
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* The Debug Bus -- implemented as a generic Decoupled IO with request
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* and response channels
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* The System Bus -- implemented as Uncached Tile Link.
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* The System Bus -- implemented as generic RegisterRouter
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*
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* DebugModule is responsible for holding registers, RAM, and ROM
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* to support debug interactions, as well as driving interrupts
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@ -321,10 +343,9 @@ class DebugBusIO(implicit val p: cde.Parameters) extends ParameterizedBundle()(p
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* It is also responsible for some reset lines.
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*/
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class DebugModule ()(implicit val p:cde.Parameters)
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extends Module
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with HasTileLinkParameters {
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val cfg = p(DMKey)
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trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
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val io: DebugModuleBundle
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//--------------------------------------------------------------
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// Import constants for shorter variable names
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@ -344,6 +365,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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require (cfg.hasBusMaster == false)
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require (cfg.nDebugRamBytes <= 64)
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require (cfg.authType == DebugModuleAuthType.None)
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require((DbBusConsts.dbRamWordBits % 8) == 0)
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//--------------------------------------------------------------
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// Private Classes (Register Fields)
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@ -403,17 +425,6 @@ class DebugModule ()(implicit val p:cde.Parameters)
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}
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//--------------------------------------------------------------
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// Module I/O
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//--------------------------------------------------------------
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val io = new Bundle {
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val db = new DebugBusIO()(p).flip()
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val debugInterrupts = Vec(cfg.nComponents, Bool()).asOutput
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val tl = new ClientUncachedTileLinkIO().flip
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val ndreset = Bool(OUTPUT)
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val fullreset = Bool(OUTPUT)
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}
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//--------------------------------------------------------------
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// Register & Wire Declarations
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@ -455,47 +466,21 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// --- Debug RAM
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// Since the access size from Debug Bus and System Bus may not be consistent,
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// use the maximum to build the RAM, and then select as needed for the smaller
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// size.
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val ramDataWidth = DbBusConsts.dbRamWordBits
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val ramDataBytes = ramDataWidth / 8;
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val ramAddrWidth = log2Up(cfg.nDebugRamBytes / ramDataBytes)
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val dbRamDataWidth = DbBusConsts.dbRamWordBits
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val sbRamDataWidth = tlDataBits
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val dbRamAddrWidth = log2Up((cfg.nDebugRamBytes * 8) / dbRamDataWidth)
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val sbRamAddrWidth = log2Up((cfg.nDebugRamBytes * 8) / sbRamDataWidth)
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val sbRamAddrOffset = log2Up(tlDataBits/8)
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val ramMem = Reg(init = Vec.fill(cfg.nDebugRamBytes){UInt(0, width = 8)})
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val ramDataWidth = dbRamDataWidth max sbRamDataWidth
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val ramAddrWidth = dbRamAddrWidth min sbRamAddrWidth
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val ramMem = Mem(1 << ramAddrWidth , UInt(width=ramDataWidth))
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val ramAddr = Wire(UInt(width=ramAddrWidth))
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val ramRdData = Wire(UInt(width=ramDataWidth))
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val ramWrData = Wire(UInt(width=ramDataWidth))
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val ramWrMask = Wire(UInt(width=ramDataWidth))
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val ramWrEn = Wire(Bool())
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val dbRamAddr = Wire(UInt(width=dbRamAddrWidth))
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val dbRamAddr = Wire(UInt(width=ramAddrWidth))
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val dbRamAddrValid = Wire(Bool())
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val dbRamRdData = Wire (UInt(width=dbRamDataWidth))
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val dbRamWrData = Wire(UInt(width=dbRamDataWidth))
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val dbRamRdData = Wire (UInt(width=ramDataWidth))
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val dbRamWrData = Wire(UInt(width=ramDataWidth))
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val dbRamWrEn = Wire(Bool())
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val dbRamRdEn = Wire(Bool())
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val dbRamWrEnFinal = Wire(Bool())
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val dbRamRdEnFinal = Wire(Bool())
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val sbRamAddr = Wire(UInt(width=sbRamAddrWidth))
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val sbRamAddrValid = Wire(Bool())
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val sbRamRdData = Wire (UInt(width=sbRamDataWidth))
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val sbRamWrData = Wire(UInt(width=sbRamDataWidth))
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val sbRamWrEn = Wire(Bool())
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val sbRamRdEn = Wire(Bool())
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val sbRamWrEnFinal = Wire(Bool())
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val sbRamRdEnFinal = Wire(Bool())
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val sbRomRdData = Wire(UInt(width=tlDataBits))
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val sbRomAddrOffset = log2Up(tlDataBits/8)
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// --- Debug Bus Accesses
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val dbRdEn = Wire(Bool())
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@ -513,16 +498,6 @@ class DebugModule ()(implicit val p:cde.Parameters)
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val rdCondWrFailure = Wire(Bool())
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val dbWrNeeded = Wire(Bool())
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// --- System Bus Access
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val sbAddr = Wire(UInt(width=sbAddrWidth))
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val sbRdData = Wire(UInt(width=tlDataBits))
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val sbWrData = Wire(UInt(width=tlDataBits))
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val sbWrMask = Wire(UInt(width=tlDataBits))
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val sbWrEn = Wire(Bool())
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val sbRdEn = Wire(Bool())
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val stallFromDb = Wire(Bool())
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val stallFromSb = Wire(Bool())
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//--------------------------------------------------------------
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// Interrupt Registers
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//--------------------------------------------------------------
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@ -622,63 +597,32 @@ class DebugModule ()(implicit val p:cde.Parameters)
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HALTSUMRdData.acks := haltnotSummary
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//--------------------------------------------------------------
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// Debug RAM Access (Debug Bus & System Bus)
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// Debug RAM Access (Debug Bus ... System Bus can override)
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//--------------------------------------------------------------
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dbReq := io.db.req.bits
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// Debug Bus RAM Access
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// From Specification: Debug RAM is 0x00 - 0x0F
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// 0x40 - 0x6F Not Implemented
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dbRamAddr := dbReq.addr( dbRamAddrWidth-1 , 0)
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dbRamAddr := dbReq.addr( ramAddrWidth-1 , 0)
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dbRamWrData := dbReq.data
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dbRamAddrValid := Bool(true)
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if (dbRamAddrWidth < 4){
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dbRamAddrValid := (dbReq.addr(3, dbRamAddrWidth) === UInt(0))
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if (ramAddrWidth < 4){
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dbRamAddrValid := (dbReq.addr(3, ramAddrWidth) === UInt(0))
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}
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sbRamAddr := sbAddr(sbRamAddrWidth + sbRamAddrOffset - 1, sbRamAddrOffset)
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sbRamWrData := sbWrData
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sbRamAddrValid := Bool(true)
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// From Specification: Debug RAM is 0x400 - 0x4FF
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if ((sbRamAddrWidth + sbRamAddrOffset) < 8){
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sbRamAddrValid := (sbAddr(7, sbRamAddrWidth + sbRamAddrOffset) === UInt(0))
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val dbRamRdDataFields = List.tabulate(cfg.nDebugRamBytes / ramDataBytes) { ii =>
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val slice = ramMem.slice(ii * ramDataBytes, (ii+1)*ramDataBytes)
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slice.reduce[UInt]{ case (x: UInt, y: UInt) => Cat(y, x)}
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}
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require (dbRamAddrWidth >= ramAddrWidth) // SB accesses less than 32 bits Not Implemented.
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val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
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dbRamRdData := dbRamRdDataFields(dbRamAddr)
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if (dbRamDataWidth < ramDataWidth){
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val dbRamSel = dbRamAddr(dbRamAddrWidth - ramAddrWidth - 1 , 0)
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val rdDataWords = Vec.tabulate(1 << (dbRamAddrWidth - ramAddrWidth)){ ii =>
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ramRdData((ii+1)*dbRamDataWidth - 1 , ii*dbRamDataWidth)}
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dbRamWrMask := Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){UInt(0, width = dbRamDataWidth)}
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dbRamWrMask(dbRamSel) := Fill(dbRamDataWidth, UInt(1, width=1))
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dbRamRdData := rdDataWords(dbRamSel)
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} else {
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dbRamRdData := ramRdData
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when (dbRamWrEnFinal) {
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for (ii <- 0 until ramDataBytes) {
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ramMem(dbRamAddr * UInt(ramDataBytes) + UInt(ii)) := dbRamWrData((8*(ii+1)-1), (8*ii))
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}
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}
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sbRamRdData := ramRdData
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ramWrMask := Mux(sbRamWrEn, sbWrMask, dbRamWrMask.asUInt)
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assert (!((dbRamWrEn | dbRamRdEn) & (sbRamRdEn | sbRamWrEn)), "Stall logic should have prevented concurrent SB/DB RAM Access")
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// Make copies of DB RAM data before writing.
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val dbRamWrDataVec = Fill(1 << (dbRamAddrWidth - ramAddrWidth), dbRamWrData)
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ramWrData := Mux(sbRamWrEn,
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(ramWrMask & sbRamWrData ) | (~ramWrMask & ramRdData),
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(ramWrMask & dbRamWrDataVec) | (~ramWrMask & ramRdData))
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ramAddr := Mux(sbRamWrEn | sbRamRdEn, sbRamAddr,
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dbRamAddr >> (dbRamAddrWidth - ramAddrWidth))
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ramRdData := ramMem(ramAddr)
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when (ramWrEn) { ramMem(ramAddr) := ramWrData }
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ramWrEn := sbRamWrEnFinal | dbRamWrEnFinal
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//--------------------------------------------------------------
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// Debug Bus Access
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@ -813,8 +757,8 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// -----------------------------------------
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// DB Access State Machine Decode (Combo)
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io.db.req.ready := !stallFromSb && ((dbStateReg === s_DB_READY) ||
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(dbStateReg === s_DB_RESP && io.db.resp.fire()))
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io.db.req.ready := (dbStateReg === s_DB_READY) ||
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(dbStateReg === s_DB_RESP && io.db.resp.fire())
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io.db.resp.valid := (dbStateReg === s_DB_RESP)
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io.db.resp.bits := dbRespReg
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@ -844,172 +788,37 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// Debug ROM
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//--------------------------------------------------------------
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sbRomRdData := UInt(0)
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if (cfg.hasDebugRom) {
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val romRegFields = if (cfg.hasDebugRom) {
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// Inspired by ROMSlave
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val romContents = cfg.debugRomContents.get
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val romByteWidth = tlDataBits / 8
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val romByteWidth = ramDataWidth / 8
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val romRows = (romContents.size + romByteWidth - 1)/romByteWidth
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val romMem = Vec.tabulate(romRows) { ii =>
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List.tabulate(romRows) { ii => {
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val slice = romContents.slice(ii*romByteWidth, (ii+1)*romByteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8)
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val line = UInt(slice.foldRight(BigInt(0)) { case (x,y) => ((y << 8) + (x.toInt & 0xFF))}, width = romByteWidth*8)
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RegField.r(ramDataWidth, line)
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}
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val sbRomRdAddr = Wire(UInt())
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if (romRows == 1) {
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sbRomRdAddr := UInt(0)
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} else {
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sbRomRdAddr := sbAddr(log2Up(romRows) + sbRomAddrOffset - 1, sbRomAddrOffset)
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}
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sbRomRdData := romMem (sbRomRdAddr)
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} else {
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Seq(RegField(ramDataWidth))
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}
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//--------------------------------------------------------------
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// System Bus Access
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//--------------------------------------------------------------
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// -----------------------------------------
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// SB Access Write Decoder
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sbRamWrEn := Bool(false)
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sbRamWrEnFinal := Bool(false)
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SETHALTNOTWrEn := Bool(false)
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CLEARDEBINTWrEn := Bool(false)
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if (tlDataBits == 32) {
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SETHALTNOTWrData := sbWrData
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CLEARDEBINTWrData := sbWrData
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when (sbAddr(11, 8) === UInt(4)){ // 0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr === SETHALTNOT){
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SETHALTNOTWrEn := sbWrEn
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}.elsewhen (sbAddr === CLEARDEBINT){
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CLEARDEBINTWrEn := sbWrEn
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}.otherwise {
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//Other registers/RAM are Not Implemented.
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}
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} else {
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// Pick out the correct word based on the address.
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val sbWrDataWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrData((ii+1)*32 - 1, ii*32)}
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val sbWrMaskWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrMask ((ii+1)*32 -1, ii*32)}
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val sbWrSelTop = log2Up(tlDataBits/8) - 1
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val sbWrSelBottom = 2
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SETHALTNOTWrData := sbWrDataWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))
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CLEARDEBINTWrData := sbWrDataWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom))
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when (sbAddr(11,8) === UInt(4)){ //0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid){
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}
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SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
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(sbWrMaskWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))).orR &&
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sbWrEn
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CLEARDEBINTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === CLEARDEBINT(sbAddrWidth-1, sbWrSelTop + 1) &&
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(sbWrMaskWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom))).orR &&
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sbWrEn
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// Local reg mapper function : Notify when written, but give the value.
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def wValue (n: Int, value: UInt, set: Bool) : RegField = {
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RegField(n, value, RegWriteFn((valid, data) => {set := valid ; value := data; Bool(true)}))
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}
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// -----------------------------------------
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// SB Access Read Mux
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sbRdData := UInt(0)
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sbRamRdEn := Bool(false)
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sbRamRdEnFinal := Bool(false)
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when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRdData := sbRamRdData
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
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if (cfg.hasDebugRom) {
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sbRdData := sbRomRdData
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} else {
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sbRdData := UInt(0)
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}
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}. otherwise {
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// All readable registers are Not Implemented.
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sbRdData := UInt(0)
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}
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// -----------------------------------------
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// SB Access State Machine -- based on BRAM Slave
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val sbAcqReg = Reg(io.tl.acquire.bits)
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val sbAcqValidReg = Reg(init = Bool(false))
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val (sbReg_get :: sbReg_getblk :: sbReg_put :: sbReg_putblk :: Nil) = Seq(
|
||||
Acquire.getType, Acquire.getBlockType, Acquire.putType, Acquire.putBlockType
|
||||
).map(sbAcqReg.isBuiltInType _)
|
||||
|
||||
val sbMultibeat = sbReg_getblk & sbAcqValidReg;
|
||||
|
||||
val sbBeatInc1 = sbAcqReg.addr_beat + UInt(1)
|
||||
|
||||
val sbLast = (sbAcqReg.addr_beat === UInt(tlDataBeats - 1))
|
||||
|
||||
sbAddr := sbAcqReg.full_addr()
|
||||
sbRdEn := (sbAcqValidReg && (sbReg_get || sbReg_getblk))
|
||||
sbWrEn := (sbAcqValidReg && (sbReg_put || sbReg_putblk))
|
||||
sbWrData := sbAcqReg.data
|
||||
sbWrMask := sbAcqReg.full_wmask()
|
||||
|
||||
// -----------------------------------------
|
||||
// SB Access State Machine Update (Seq)
|
||||
|
||||
when (io.tl.acquire.fire()){
|
||||
sbAcqReg := io.tl.acquire.bits
|
||||
sbAcqValidReg := Bool(true)
|
||||
} .elsewhen (io.tl.grant.fire()) {
|
||||
when (sbMultibeat){
|
||||
sbAcqReg.addr_beat := sbBeatInc1
|
||||
when (sbLast) {
|
||||
sbAcqValidReg := Bool(false)
|
||||
}
|
||||
} . otherwise {
|
||||
sbAcqValidReg := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
io.tl.grant.valid := sbAcqValidReg
|
||||
io.tl.grant.bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = sbAcqReg.getBuiltInGrantType(),
|
||||
client_xact_id = sbAcqReg.client_xact_id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = sbAcqReg.addr_beat,
|
||||
data = sbRdData
|
||||
regmap(
|
||||
CLEARDEBINT -> Seq(wValue(sbIdWidth, CLEARDEBINTWrData, CLEARDEBINTWrEn)),
|
||||
SETHALTNOT -> Seq(wValue(sbIdWidth, SETHALTNOTWrData, SETHALTNOTWrEn)),
|
||||
RAMBASE -> ramMem.map(x => RegField(8, x)),
|
||||
ROMBASE -> romRegFields
|
||||
)
|
||||
|
||||
stallFromDb := Bool(false) // SB always wins, and DB latches its read data so it is not necessary for SB to wait
|
||||
|
||||
stallFromSb := sbRamRdEn || sbRamWrEn // pessimistically assume that DB/SB are going to conflict on the RAM,
|
||||
// and SB doesn't latch its read data to it is necessary for DB hold
|
||||
// off while SB is accessing the RAM and waiting to send its result.
|
||||
|
||||
val sbStall = (sbMultibeat & !sbLast) || (io.tl.grant.valid && !io.tl.grant.ready) || stallFromDb
|
||||
|
||||
io.tl.acquire.ready := !sbStall
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Misc. Outputs
|
||||
//--------------------------------------------------------------
|
||||
@ -1019,6 +828,21 @@ class DebugModule ()(implicit val p:cde.Parameters)
|
||||
|
||||
}
|
||||
|
||||
/** Create a concrete TL2 Slave for the DebugModule RegMapper interface.
|
||||
*
|
||||
*/
|
||||
|
||||
class TLDebugModule(beatBytes: Int) (implicit p: Parameters)
|
||||
extends TLRegisterRouter(0x0, beatBytes=beatBytes)(
|
||||
new TLRegBundle(p, _ ) with DebugModuleBundle)(
|
||||
new TLRegModule(p, _, _) with DebugModule)
|
||||
|
||||
|
||||
/** Synchronizers for DebugBus
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
object AsyncDebugBusCrossing {
|
||||
// takes from_source from the 'from' clock domain to the 'to' clock domain
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, to_clock: Clock, to_reset: Bool, depth: Int = 1, sync: Int = 3) = {
|
||||
@ -1029,6 +853,7 @@ object AsyncDebugBusCrossing {
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
object AsyncDebugBusFrom { // OutsideClockDomain
|
||||
// takes from_source from the 'from' clock domain and puts it into your clock domain
|
||||
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, depth: Int = 1, sync: Int = 3): DebugBusIO = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user