riscv/rocket-chip
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Chisel3 has different Vec semantics

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Vec(a, b) := c doesn't modify a and b in chisel3.
This commit is contained in:
Andrew Waterman 2015-08-03 19:08:00 -07:00
parent c345d72af4
commit d4c94c6566
1 changed files with 4 additions and 3 deletions
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7
rocket/src/main/scala/idecode.scala
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@ -55,9 +55,10 @@ class IntCtrlSigs extends Bundle {
def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = DecodeLogic(inst, XDecode.decode_default, table) val decoder = DecodeLogic(inst, XDecode.decode_default, table)
Vec(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo) := decoder rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo)
sigs zip decoder map {case(s,d) => s := d}
this this
} }
} }