From d4c94c6566111b34b632d65eaeaad47fb5f8f3d3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 3 Aug 2015 19:08:00 -0700 Subject: [PATCH] Chisel3 has different Vec semantics Vec(a, b) := c doesn't modify a and b in chisel3. --- rocket/src/main/scala/idecode.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/idecode.scala b/rocket/src/main/scala/idecode.scala index 97058bd4..2464b817 100644 --- a/rocket/src/main/scala/idecode.scala +++ b/rocket/src/main/scala/idecode.scala @@ -55,9 +55,10 @@ class IntCtrlSigs extends Bundle { def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = DecodeLogic(inst, XDecode.decode_default, table) - Vec(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, - sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, - rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo) := decoder + val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, + sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, + rfs1, rfs2, rfs3, wfd, div, wxd, csr, fence_i, fence, amo) + sigs zip decoder map {case(s,d) => s := d} this } }