riscv/rocket-chip
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Abstract base nbcache class

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This commit is contained in:
Henry Cook 2012-02-16 12:34:51 -08:00
parent 124efe5281
commit d46e59a16d
2 changed files with 13 additions and 2 deletions
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13
rocket/src/main/scala/nbdcache.scala
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@ -684,7 +684,18 @@ class ioDCache(view: List[String] = null) extends Bundle(view) {
val resp_val = Bool(OUTPUT); val resp_val = Bool(OUTPUT);
} }
class HellaCache extends Component with ThreeStateIncoherence { abstract class HellaCache extends Component {
def isHit ( cmd: Bits, state: UFix): Bool
def isValid (state: UFix): Bool
def needsWriteback (state: UFix): Bool
def newStateOnWriteback(): UFix
def newStateOnFlush(): UFix
def newStateOnHit(cmd: Bits, state: UFix): UFix
def newStateOnPrimaryMiss(cmd: Bits): UFix
def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
}
class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
val io = new Bundle { val io = new Bundle {
val cpu = new ioDmem() val cpu = new ioDmem()
val mem = new ioDCache().flip val mem = new ioDCache().flip

2
rocket/src/main/scala/top.scala
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@ -18,7 +18,7 @@ class Top() extends Component {
val icache = new rocketICache(128, 2); // 128 sets x 2 ways val icache = new rocketICache(128, 2); // 128 sets x 2 ways
val icache_pf = new rocketIPrefetcher(); val icache_pf = new rocketIPrefetcher();
val vicache = new rocketICache(128, 2); // 128 sets x 2 ways val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
val dcache = new HellaCache(); val dcache = new HellaCacheUniproc();
val arbiter = new rocketMemArbiter(); val arbiter = new rocketMemArbiter();
arbiter.io.mem <> io.mem; arbiter.io.mem <> io.mem;