From d46e59a16de4e51bd08025b53fcf178a73bd9317 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Thu, 16 Feb 2012 12:34:51 -0800
Subject: [PATCH] Abstract base nbcache class

---
 rocket/src/main/scala/nbdcache.scala | 13 ++++++++++++-
 rocket/src/main/scala/top.scala      |  2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 41a22728..42d402e3 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -684,7 +684,18 @@ class ioDCache(view: List[String] = null) extends Bundle(view) {
   val resp_val  = Bool(OUTPUT);
 }
  
-class HellaCache extends Component with ThreeStateIncoherence {
+abstract class HellaCache extends Component {
+  def isHit ( cmd: Bits, state: UFix): Bool
+  def isValid (state: UFix): Bool
+  def needsWriteback (state: UFix): Bool
+  def newStateOnWriteback(): UFix
+  def newStateOnFlush(): UFix
+  def newStateOnHit(cmd: Bits, state: UFix): UFix
+  def newStateOnPrimaryMiss(cmd: Bits): UFix
+  def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
+}
+
+class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
   val io = new Bundle {
     val cpu = new ioDmem()
     val mem = new ioDCache().flip
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 92c6b9dc..ec40a7c7 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -18,7 +18,7 @@ class Top() extends Component {
   val icache    = new rocketICache(128, 2); // 128 sets x 2 ways
   val icache_pf = new rocketIPrefetcher();
   val vicache   = new rocketICache(128, 2); // 128 sets x 2 ways
-  val dcache    = new HellaCache();
+  val dcache    = new HellaCacheUniproc();
   val arbiter   = new rocketMemArbiter();
 
   arbiter.io.mem    <> io.mem;