README updated for new fpga flow

2014-08-07 14:52:56 -07:00
parent e390eba8ce
commit d3a8a224fe
1 changed files with 5 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -58,6 +58,11 @@ And to run the assembly tests on the C simulator and generate waveforms:
    $ make run-vecasm-timer-tests-debug
    $ make run-bmarks-test-debug

+To FPGA-synthesizable verilog (output will be in `/fpga/generated-src`):
+
+    $ cd fpga/build/syn
+    $ make
+

 Updating To A Newer Version Of Chisel
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