From d3a8a224fec0f9be237ab08f9364939ada99c563 Mon Sep 17 00:00:00 2001
From: Scott Beamer <sbeamer@eecs.berkeley.edu>
Date: Thu, 7 Aug 2014 14:52:56 -0700
Subject: [PATCH] README updated for new fpga flow

---
 README.md | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/README.md b/README.md
index ff2ef41a..efa2c547 100644
--- a/README.md
+++ b/README.md
@@ -58,6 +58,11 @@ And to run the assembly tests on the C simulator and generate waveforms:
     $ make run-vecasm-timer-tests-debug
     $ make run-bmarks-test-debug
 
+To FPGA-synthesizable verilog (output will be in `/fpga/generated-src`):
+
+    $ cd fpga/build/syn
+    $ make
+
 
 Updating To A Newer Version Of Chisel
 -------------------------------------