riscv/rocket-chip
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Clean up handling of icache's io.cpu.npc signal

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This commit is contained in:
Andrew Waterman 2015-05-18 18:22:48 -07:00
parent b09832f1b5
commit d31b26c342
2 changed files with 6 additions and 5 deletions
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1
rocket/src/main/scala/core.scala
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@ -40,6 +40,7 @@ abstract trait CoreParameters extends UsesParameters {
val coreDataBytes = coreDataBits/8 val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = params(CoreDCacheReqTagBits) val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
if(params(FastLoadByte)) require(params(FastLoadWord)) if(params(FastLoadByte)) require(params(FastLoadWord))
} }

10
rocket/src/main/scala/icache.scala
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@ -16,11 +16,11 @@ abstract class FrontendBundle extends Bundle with FrontendParameters
abstract class FrontendModule extends Module with FrontendParameters abstract class FrontendModule extends Module with FrontendParameters
class FrontendReq extends CoreBundle { class FrontendReq extends CoreBundle {
val pc = UInt(width = vaddrBits+1) val pc = UInt(width = vaddrBitsExtended)
} }
class FrontendResp extends CoreBundle { class FrontendResp extends CoreBundle {
val pc = UInt(width = vaddrBits+1) // ID stage PC val pc = UInt(width = vaddrBitsExtended) // ID stage PC
val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits)) val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
val mask = Bits(width = coreFetchWidth) val mask = Bits(width = coreFetchWidth)
val xcpt_if = Bool() val xcpt_if = Bool()
@ -34,7 +34,7 @@ class CPUFrontendIO extends CoreBundle {
val bht_update = Valid(new BHTUpdate) val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate) val ras_update = Valid(new RASUpdate)
val invalidate = Bool(OUTPUT) val invalidate = Bool(OUTPUT)
val npc = UInt(INPUT, width = vaddrBits+1) val npc = UInt(INPUT, width = vaddrBitsExtended)
} }
class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
@ -103,8 +103,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
icache.io.mem <> io.mem icache.io.mem <> io.mem
icache.io.req.valid := !stall && !s0_same_block icache.io.req.valid := !stall && !s0_same_block
io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) icache.io.req.bits.idx := io.cpu.npc
icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
icache.io.invalidate := io.cpu.invalidate icache.io.invalidate := io.cpu.invalidate
icache.io.req.bits.ppn := tlb.io.resp.ppn icache.io.req.bits.ppn := tlb.io.resp.ppn
icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
@ -112,6 +111,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc io.cpu.resp.bits.pc := s2_pc
io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
require(coreFetchWidth * coreInstBytes <= rowBytes) require(coreFetchWidth * coreInstBytes <= rowBytes)
val fetch_data = val fetch_data =