From d31b26c342e7ef2f10fbe64597c1330d3c353269 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 18 May 2015 18:22:48 -0700
Subject: [PATCH] Clean up handling of icache's io.cpu.npc signal

---
 rocket/src/main/scala/core.scala   |  1 +
 rocket/src/main/scala/icache.scala | 10 +++++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala
index 33bb617b..d73e494d 100644
--- a/rocket/src/main/scala/core.scala
+++ b/rocket/src/main/scala/core.scala
@@ -40,6 +40,7 @@ abstract trait CoreParameters extends UsesParameters {
   val coreDataBytes = coreDataBits/8
   val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
   val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
+  val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
 
   if(params(FastLoadByte)) require(params(FastLoadWord))
 }
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 8686d310..79500260 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -16,11 +16,11 @@ abstract class FrontendBundle extends Bundle with FrontendParameters
 abstract class FrontendModule extends Module with FrontendParameters
 
 class FrontendReq extends CoreBundle {
-  val pc = UInt(width = vaddrBits+1)
+  val pc = UInt(width = vaddrBitsExtended)
 }
 
 class FrontendResp extends CoreBundle {
-  val pc = UInt(width = vaddrBits+1)  // ID stage PC
+  val pc = UInt(width = vaddrBitsExtended)  // ID stage PC
   val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
   val mask = Bits(width = coreFetchWidth)
   val xcpt_if = Bool()
@@ -34,7 +34,7 @@ class CPUFrontendIO extends CoreBundle {
   val bht_update = Valid(new BHTUpdate)
   val ras_update = Valid(new RASUpdate)
   val invalidate = Bool(OUTPUT)
-  val npc = UInt(INPUT, width = vaddrBits+1)
+  val npc = UInt(INPUT, width = vaddrBitsExtended)
 }
 
 class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
@@ -103,8 +103,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
 
   icache.io.mem <> io.mem
   icache.io.req.valid := !stall && !s0_same_block
-  io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
-  icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
+  icache.io.req.bits.idx := io.cpu.npc
   icache.io.invalidate := io.cpu.invalidate
   icache.io.req.bits.ppn := tlb.io.resp.ppn
   icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
@@ -112,6 +111,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
 
   io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
   io.cpu.resp.bits.pc := s2_pc
+  io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
 
   require(coreFetchWidth * coreInstBytes <= rowBytes)
   val fetch_data =