Merge pull request #1239 from freechipsproject/reduce_debug_flags

Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
parent bb1976552f d72abb7a12
commit cf7cd03d64
4 changed files with 16 additions and 5 deletions
--- a/src/main/scala/tilelink/RegisterRouter.scala
+++ b/src/main/scala/tilelink/RegisterRouter.scala
@ -111,7 +111,12 @@ case class TLRegisterNode(
      ("baseAddress" -> base) ~
      ("regfields" -> regDescs)
    ))
-    ElaborationArtefacts.add(s"${base}.regmap.json", pretty(render(json)))
+
+    var suffix = 0
+    while( ElaborationArtefacts.contains(s"${base}.${suffix}.regmap.json")){
+      suffix = suffix + 1
+    }
+    ElaborationArtefacts.add(s"${base}.${suffix}.regmap.json", pretty(render(json)))
  }
 }