diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index 5e0c3fc6..e34ed3be 100644
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -785,7 +785,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
       val go = Bool()
     }
 
-    val flags = Wire(init = Vec.fill(1024){new flagBundle().fromBits(0.U)})
+    val flags = Wire(init = Vec.fill(nComponents){new flagBundle().fromBits(0.U)})
     assert ((cfg.hartSelToHartId(selectedHartReg) < 1024.U),
       "HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work.");
     flags(cfg.hartSelToHartId(selectedHartReg)).go := goReg
@@ -904,9 +904,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
       ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
         abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", ""))}),
       FLAGS         -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
-        flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_$i", ""))}),
+        flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_${i}", ""))}),
       ROMBASE       -> RegFieldGroup("debug_rom", Some("Debug ROM"),
-        DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
+        DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W),
+          RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
     )
 
     // Override System Bus accesses with dmactive reset.
diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala
index 0f5e64cc..d676ec79 100644
--- a/src/main/scala/regmapper/RegField.scala
+++ b/src/main/scala/regmapper/RegField.scala
@@ -164,7 +164,7 @@ object RegField
     val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
     when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
     Seq.tabulate(numBytes) { i =>
-      val newDesc = desc.map {d => d.copy(name = d.name + s"[${(i+1)*8-1}:${i*8}]")}
+      val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")}
       RegField(8, oldBytes(i),
         RegWriteFn((valid, data) => {
         valids(i) := valid
diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala
index 2d99a693..b194d8f5 100644
--- a/src/main/scala/tilelink/RegisterRouter.scala
+++ b/src/main/scala/tilelink/RegisterRouter.scala
@@ -111,7 +111,12 @@ case class TLRegisterNode(
       ("baseAddress" -> base) ~
       ("regfields" -> regDescs)
     ))
-    ElaborationArtefacts.add(s"${base}.regmap.json", pretty(render(json)))
+
+    var suffix = 0
+    while( ElaborationArtefacts.contains(s"${base}.${suffix}.regmap.json")){
+      suffix = suffix + 1
+    }
+    ElaborationArtefacts.add(s"${base}.${suffix}.regmap.json", pretty(render(json)))
   }
 }
 
diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala
index c7830ddf..18b1a9b7 100644
--- a/src/main/scala/util/GeneratorUtils.scala
+++ b/src/main/scala/util/GeneratorUtils.scala
@@ -139,7 +139,12 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
 
 object ElaborationArtefacts {
   var files: Seq[(String, () => String)] = Nil
+
   def add(extension: String, contents: => String) {
     files = (extension, () => contents) +: files
   }
+
+  def contains(extension: String): Boolean = {
+    files.foldLeft(false)((t, s) => {s._1 == extension | t})
+  }
 }