renamed SRAM modules to match TSMC65 MC generated SRAMs
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@ -249,16 +249,18 @@ class rocketDCacheDM(lines: Int) extends Component {
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((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) ||
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((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) ||
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((state === s_resolve_miss) && r_req_flush);
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((state === s_resolve_miss) && r_req_flush);
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val tag_array = new rocketSRAMsp(lines, tagbits);
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// val tag_array = new rocketSRAMsp(lines, tagbits);
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val tag_array = new TS1N65LPA128X27M4;
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tag_array.io.a := tag_addr;
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tag_array.io.a := tag_addr;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.we := tag_we;
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tag_array.io.web := ~tag_we;
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.bweb := Bits(0,tagbits);
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tag_array.io.ce :=
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tag_array.io.ceb := !(
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(io.cpu.req_val && io.cpu.req_rdy) ||
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(io.cpu.req_val && io.cpu.req_rdy) ||
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(state === s_start_writeback) ||
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(state === s_start_writeback) ||
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(state === s_writeback);
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(state === s_writeback));
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val tag_rdata = tag_array.io.q;
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val tag_rdata = tag_array.io.q;
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tag_array.io.tsel := Bits(1,2);
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// valid bit array
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_array = Reg(resetVal = Bits(0, lines));
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@ -331,7 +333,8 @@ class rocketDCacheDM(lines: Int) extends Component {
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val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d));
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val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d));
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// data array
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// data array
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val data_array = new rocketSRAMsp(lines*4, 128);
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// val data_array = new rocketSRAMsp(lines*4, 128);
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val data_array = new TS1N65LPA512X128M4;
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val data_array_rdata = data_array.io.q;
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val data_array_rdata = data_array.io.q;
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val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
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val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
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val r_resp_data = Reg(resp_data);
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val r_resp_data = Reg(resp_data);
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@ -372,23 +375,24 @@ class rocketDCacheDM(lines: Int) extends Component {
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Mux((state === s_write_amo), amo_alu_out,
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Mux((state === s_write_amo), amo_alu_out,
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store_data));
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store_data));
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data_array.io.we :=
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data_array.io.web := !(
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((state === s_refill) && io.mem.resp_val) ||
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((state === s_refill) && io.mem.resp_val) ||
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(state === s_write_amo) ||
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(state === s_write_amo) ||
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drain_store || resolve_store;
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drain_store || resolve_store);
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data_array.io.bweb :=
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data_array.io.bweb := ~(
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Mux((state === s_refill), ~Bits(0,128),
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Mux((state === s_refill), ~Bits(0,128),
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Mux((state === s_write_amo), amo_store_wmask,
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Mux((state === s_write_amo), amo_store_wmask,
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store_wmask));
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store_wmask)));
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data_array.io.ce :=
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data_array.io.ceb := !(
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(io.cpu.req_val && io.cpu.req_rdy && (req_load || req_amo)) ||
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(io.cpu.req_val && io.cpu.req_rdy && (req_load || req_amo)) ||
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(state === s_start_writeback) ||
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(state === s_start_writeback) ||
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(state === s_writeback) ||
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(state === s_writeback) ||
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((state === s_resolve_miss) && (r_req_load || r_req_amo)) ||
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((state === s_resolve_miss) && (r_req_load || r_req_amo)) ||
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(state === s_replay_load);
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(state === s_replay_load));
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data_array.io.tsel := Bits(1,2);
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// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
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// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
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// (causes the cache to block for 2 cycles and the load or amo instruction is replayed)
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// (causes the cache to block for 2 cycles and the load or amo instruction is replayed)
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val load_miss =
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val load_miss =
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@ -39,12 +39,33 @@ class ioSRAMsp (width: Int, addrbits: Int) extends Bundle {
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val a = UFix(addrbits, 'input); // address
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val a = UFix(addrbits, 'input); // address
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val d = Bits(width, 'input); // data input
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val d = Bits(width, 'input); // data input
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val bweb = Bits(width, 'input); // bit write enable mask
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val bweb = Bits(width, 'input); // bit write enable mask
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val ce = Bool('input); // chip enable
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val ceb = Bool('input); // chip enable
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val we = Bool('input); // write enable
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val web = Bool('input); // write enable
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val q = Bits(width, 'output); // data out
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val q = Bits(width, 'output); // data out
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val tsel = Bits(2, 'input);
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}
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}
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// single ported SRAM
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// single ported SRAM
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class TS1N65LPA128X27M4 extends Component {
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val addrbits = 7;
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val width = 27;
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val entries = 128;
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val io = new ioSRAMsp(width, addrbits);
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val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
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val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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}
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class TS1N65LPA512X128M4 extends Component {
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val addrbits = 9;
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val width = 128;
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val entries = 512;
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val io = new ioSRAMsp(width, addrbits);
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val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
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val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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}
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/*
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class rocketSRAMsp(entries: Int, width: Int) extends Component {
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class rocketSRAMsp(entries: Int, width: Int) extends Component {
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val addrbits = ceil(log10(entries)/log10(2)).toInt;
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val addrbits = ceil(log10(entries)/log10(2)).toInt;
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val io = new ioSRAMsp(width, addrbits);
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val io = new ioSRAMsp(width, addrbits);
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@ -52,6 +73,7 @@ class rocketSRAMsp(entries: Int, width: Int) extends Component {
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val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width)));
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val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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io.q := rdata;
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}
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}
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*/
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// basic direct mapped instruction cache
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// basic direct mapped instruction cache
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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@ -99,16 +121,18 @@ class rocketICacheDM(lines: Int) extends Component {
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}
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}
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// tag array
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// tag array
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val tag_array = new rocketSRAMsp(lines, tagbits);
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// val tag_array = new rocketSRAMsp(lines, tagbits);
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val tag_array = new TS1N65LPA128X27M4;
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val tag_addr =
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val tag_addr =
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Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
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Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
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io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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tag_array.io.a := tag_addr;
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tag_array.io.a := tag_addr;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.we := tag_we;
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tag_array.io.web := ~tag_we;
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tag_array.io.bweb := ~Bits(0,tagbits);
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tag_array.io.tsel := Bits(1,2);
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tag_array.io.ce := (io.cpu.req_val && io.cpu.req_rdy);
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tag_array.io.bweb := Bits(0,tagbits);
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tag_array.io.ceb := !(io.cpu.req_val && io.cpu.req_rdy);
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val tag_rdata = tag_array.io.q;
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val tag_rdata = tag_array.io.q;
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// valid bit array
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// valid bit array
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@ -124,14 +148,16 @@ class rocketICacheDM(lines: Int) extends Component {
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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// data array
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// data array
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val data_array = new rocketSRAMsp(lines*4, 128);
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// val data_array = new rocketSRAMsp(lines*4, 128);
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val data_array = new TS1N65LPA512X128M4;
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data_array.io.a :=
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data_array.io.a :=
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
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data_array.io.d := io.mem.resp_data;
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data_array.io.d := io.mem.resp_data;
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data_array.io.we := io.mem.resp_val;
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data_array.io.web := ~io.mem.resp_val;
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data_array.io.bweb := ~Bits(0,128);
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data_array.io.bweb := Bits(0,128);
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data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss);
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data_array.io.tsel := Bits(1,2);
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data_array.io.ceb := !((io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss));
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val data_array_rdata = data_array.io.q;
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val data_array_rdata = data_array.io.q;
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