From cf1965493bcd5019e908322f5ec3938cf9b68b37 Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Thu, 1 Dec 2011 13:14:33 -0800 Subject: [PATCH] renamed SRAM modules to match TSMC65 MC generated SRAMs --- rocket/src/main/scala/dcache.scala | 28 +++++++++-------- rocket/src/main/scala/icache.scala | 48 +++++++++++++++++++++++------- 2 files changed, 53 insertions(+), 23 deletions(-) diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 1fcda1a5..d9872515 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -249,16 +249,18 @@ class rocketDCacheDM(lines: Int) extends Component { ((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) || ((state === s_resolve_miss) && r_req_flush); - val tag_array = new rocketSRAMsp(lines, tagbits); +// val tag_array = new rocketSRAMsp(lines, tagbits); + val tag_array = new TS1N65LPA128X27M4; tag_array.io.a := tag_addr; tag_array.io.d := r_cpu_req_ppn; - tag_array.io.we := tag_we; - tag_array.io.bweb := ~Bits(0,tagbits); - tag_array.io.ce := + tag_array.io.web := ~tag_we; + tag_array.io.bweb := Bits(0,tagbits); + tag_array.io.ceb := !( (io.cpu.req_val && io.cpu.req_rdy) || (state === s_start_writeback) || - (state === s_writeback); + (state === s_writeback)); val tag_rdata = tag_array.io.q; + tag_array.io.tsel := Bits(1,2); // valid bit array val vb_array = Reg(resetVal = Bits(0, lines)); @@ -331,7 +333,8 @@ class rocketDCacheDM(lines: Int) extends Component { val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d)); // data array - val data_array = new rocketSRAMsp(lines*4, 128); +// val data_array = new rocketSRAMsp(lines*4, 128); + val data_array = new TS1N65LPA512X128M4; val data_array_rdata = data_array.io.q; val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0)); val r_resp_data = Reg(resp_data); @@ -372,23 +375,24 @@ class rocketDCacheDM(lines: Int) extends Component { Mux((state === s_write_amo), amo_alu_out, store_data)); - data_array.io.we := + data_array.io.web := !( ((state === s_refill) && io.mem.resp_val) || (state === s_write_amo) || - drain_store || resolve_store; + drain_store || resolve_store); - data_array.io.bweb := + data_array.io.bweb := ~( Mux((state === s_refill), ~Bits(0,128), Mux((state === s_write_amo), amo_store_wmask, - store_wmask)); + store_wmask))); - data_array.io.ce := + data_array.io.ceb := !( (io.cpu.req_val && io.cpu.req_rdy && (req_load || req_amo)) || (state === s_start_writeback) || (state === s_writeback) || ((state === s_resolve_miss) && (r_req_load || r_req_amo)) || - (state === s_replay_load); + (state === s_replay_load)); + data_array.io.tsel := Bits(1,2); // signal a load miss when the data isn't present in the cache and when it's in the pending store data register // (causes the cache to block for 2 cycles and the load or amo instruction is replayed) val load_miss = diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index a7fa954e..2d332657 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -39,19 +39,41 @@ class ioSRAMsp (width: Int, addrbits: Int) extends Bundle { val a = UFix(addrbits, 'input); // address val d = Bits(width, 'input); // data input val bweb = Bits(width, 'input); // bit write enable mask - val ce = Bool('input); // chip enable - val we = Bool('input); // write enable + val ceb = Bool('input); // chip enable + val web = Bool('input); // write enable val q = Bits(width, 'output); // data out + val tsel = Bits(2, 'input); } // single ported SRAM +class TS1N65LPA128X27M4 extends Component { + val addrbits = 7; + val width = 27; + val entries = 128; + val io = new ioSRAMsp(width, addrbits); + val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null); + val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width))); + io.q := rdata; +} + +class TS1N65LPA512X128M4 extends Component { + val addrbits = 9; + val width = 128; + val entries = 512; + val io = new ioSRAMsp(width, addrbits); + val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null); + val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width))); + io.q := rdata; +} +/* class rocketSRAMsp(entries: Int, width: Int) extends Component { val addrbits = ceil(log10(entries)/log10(2)).toInt; val io = new ioSRAMsp(width, addrbits); val sram = Mem(entries, io.we, io.a, io.d, wrMask = io.bweb, resetVal = null); val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width))); io.q := rdata; -} +} +*/ // basic direct mapped instruction cache // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines @@ -99,16 +121,18 @@ class rocketICacheDM(lines: Int) extends Component { } // tag array - val tag_array = new rocketSRAMsp(lines, tagbits); +// val tag_array = new rocketSRAMsp(lines, tagbits); + val tag_array = new TS1N65LPA128X27M4; val tag_addr = Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits), io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix; val tag_we = (state === s_refill_wait) && io.mem.resp_val; tag_array.io.a := tag_addr; tag_array.io.d := r_cpu_req_ppn; - tag_array.io.we := tag_we; - tag_array.io.bweb := ~Bits(0,tagbits); - tag_array.io.ce := (io.cpu.req_val && io.cpu.req_rdy); + tag_array.io.web := ~tag_we; + tag_array.io.tsel := Bits(1,2); + tag_array.io.bweb := Bits(0,tagbits); + tag_array.io.ceb := !(io.cpu.req_val && io.cpu.req_rdy); val tag_rdata = tag_array.io.q; // valid bit array @@ -124,14 +148,16 @@ class rocketICacheDM(lines: Int) extends Component { val tag_match = (tag_rdata === io.cpu.req_ppn); // data array - val data_array = new rocketSRAMsp(lines*4, 128); +// val data_array = new rocketSRAMsp(lines*4, 128); + val data_array = new TS1N65LPA512X128M4; data_array.io.a := Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count), io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix; data_array.io.d := io.mem.resp_data; - data_array.io.we := io.mem.resp_val; - data_array.io.bweb := ~Bits(0,128); - data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss); + data_array.io.web := ~io.mem.resp_val; + data_array.io.bweb := Bits(0,128); + data_array.io.tsel := Bits(1,2); + data_array.io.ceb := !((io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss)); val data_array_rdata = data_array.io.q;