riscv/rocket-chip
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renamed SRAM modules to match TSMC65 MC generated SRAMs

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This commit is contained in:
Rimas Avizienis
2011-12-01 13:14:33 -08:00
parent da2fdf4f85
commit cf1965493b
2 changed files with 53 additions and 23 deletions
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48
rocket/src/main/scala/icache.scala
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@ -39,19 +39,41 @@ class ioSRAMsp (width: Int, addrbits: Int) extends Bundle {
val a = UFix(addrbits, 'input); // address
val d = Bits(width, 'input); // data input
val bweb = Bits(width, 'input); // bit write enable mask
val ce = Bool('input); // chip enable
val we = Bool('input); // write enable
val ceb = Bool('input); // chip enable
val web = Bool('input); // write enable
val q = Bits(width, 'output); // data out
val tsel = Bits(2, 'input);
}
// single ported SRAM
class TS1N65LPA128X27M4 extends Component {
val addrbits = 7;
val width = 27;
val entries = 128;
val io = new ioSRAMsp(width, addrbits);
val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
io.q := rdata;
}
class TS1N65LPA512X128M4 extends Component {
val addrbits = 9;
val width = 128;
val entries = 512;
val io = new ioSRAMsp(width, addrbits);
val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
io.q := rdata;
}
/*
class rocketSRAMsp(entries: Int, width: Int) extends Component {
val addrbits = ceil(log10(entries)/log10(2)).toInt;
val io = new ioSRAMsp(width, addrbits);
val sram = Mem(entries, io.we, io.a, io.d, wrMask = io.bweb, resetVal = null);
val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width)));
io.q := rdata;
}
}
*/
// basic direct mapped instruction cache
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
@ -99,16 +121,18 @@ class rocketICacheDM(lines: Int) extends Component {
}
// tag array
val tag_array = new rocketSRAMsp(lines, tagbits);
// val tag_array = new rocketSRAMsp(lines, tagbits);
val tag_array = new TS1N65LPA128X27M4;
val tag_addr =
Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
val tag_we = (state === s_refill_wait) && io.mem.resp_val;
tag_array.io.a := tag_addr;
tag_array.io.d := r_cpu_req_ppn;
tag_array.io.we := tag_we;
tag_array.io.bweb := ~Bits(0,tagbits);
tag_array.io.ce := (io.cpu.req_val && io.cpu.req_rdy);
tag_array.io.web := ~tag_we;
tag_array.io.tsel := Bits(1,2);
tag_array.io.bweb := Bits(0,tagbits);
tag_array.io.ceb := !(io.cpu.req_val && io.cpu.req_rdy);
val tag_rdata = tag_array.io.q;
// valid bit array
@ -124,14 +148,16 @@ class rocketICacheDM(lines: Int) extends Component {
val tag_match = (tag_rdata === io.cpu.req_ppn);
// data array
val data_array = new rocketSRAMsp(lines*4, 128);
// val data_array = new rocketSRAMsp(lines*4, 128);
val data_array = new TS1N65LPA512X128M4;
data_array.io.a :=
Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
data_array.io.d := io.mem.resp_data;
data_array.io.we := io.mem.resp_val;
data_array.io.bweb := ~Bits(0,128);
data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss);
data_array.io.web := ~io.mem.resp_val;
data_array.io.bweb := Bits(0,128);
data_array.io.tsel := Bits(1,2);
data_array.io.ceb := !((io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss));
val data_array_rdata = data_array.io.q;