riscv/rocket-chip
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a few more fixes. some param lookups fail (here() in Alter blocks)

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Henry Cook 2014-08-10 23:07:15 -07:00
parent 0dac9a7467
commit ca5f38ff26
2 changed files with 3 additions and 2 deletions
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1
rocket/src/main/scala/icache.scala
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@ -19,6 +19,7 @@ class FrontendResp extends Bundle {
} }
class CPUFrontendIO extends Bundle { class CPUFrontendIO extends Bundle {
params.alter(params(CoreBTBParams))
val req = Valid(new FrontendReq) val req = Valid(new FrontendReq)
val resp = Decoupled(new FrontendResp).flip val resp = Decoupled(new FrontendResp).flip
val btb_resp = Valid(new BTBResp).flip val btb_resp = Valid(new BTBResp).flip

4
rocket/src/main/scala/tile.scala
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@ -32,8 +32,8 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
val optionalRoCC = params(BuildRoCC) val optionalRoCC = params(BuildRoCC)
params.alter(params(RocketFrontendParams)) // Used in icache, Core val p = params.alter(params(CoreBTBParams)).alter(params(RocketFrontendParams)) // Used in icache, Core
val icache = Module(new Frontend) val icache = Module(new Frontend)(p) //TODO PARAMS: best way to alter both?
params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core
val dcache = Module(new HellaCache) val dcache = Module(new HellaCache)
val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5)) val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5))