diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 0db261a1..43035d55 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -19,6 +19,7 @@ class FrontendResp extends Bundle {
 }
 
 class CPUFrontendIO extends Bundle {
+  params.alter(params(CoreBTBParams))
   val req = Valid(new FrontendReq)
   val resp = Decoupled(new FrontendResp).flip
   val btb_resp = Valid(new BTBResp).flip
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index fa048908..b7f7e412 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -32,8 +32,8 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
 
   val optionalRoCC = params(BuildRoCC)
 
-  params.alter(params(RocketFrontendParams)) // Used in icache, Core
-  val icache = Module(new Frontend)
+  val p = params.alter(params(CoreBTBParams)).alter(params(RocketFrontendParams)) // Used in icache, Core
+  val icache = Module(new Frontend)(p) //TODO PARAMS: best way to alter both?
   params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core
   val dcache = Module(new HellaCache)
   val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5))