From c9e787481891085db413eca9a15f1596e5fa83a2 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 11 Nov 2014 17:36:48 -0800
Subject: [PATCH] Major tilelink revision for uncached message types

---
 rocket/src/main/scala/icache.scala   | 4 ++--
 rocket/src/main/scala/nbdcache.scala | 6 ++----
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 45327e46..d046b858 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -258,14 +258,14 @@ class ICache extends FrontendModule
   io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
 
   val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
-  ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload.g_type)
+  ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload)
   ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
   ack_q.io.enq.bits.header.dst := refill_bits.header.src
 
   // output signals
   io.resp.valid := s2_hit
   io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
-  io.mem.acquire.bits.payload := Acquire(co.getUncachedReadAcquireType, s2_addr >> UInt(blockOffBits), UInt(0))
+  io.mem.acquire.bits.payload := UncachedRead(s2_addr >> UInt(blockOffBits))
   io.mem.finish <> ack_q.io.deq
 
   // control state machine
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 80d1a6bc..3cc3d5e1 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -254,7 +254,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
   }
 
   val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
-  ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
+  ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload)
   ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
   ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
   val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
@@ -288,9 +288,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
   io.wb_req.bits.r_type := co.getReleaseTypeOnVoluntaryWriteback()
 
   io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
-  io.mem_req.bits.a_type := acquire_type
-  io.mem_req.bits.addr := Cat(io.tag, req_idx).toUInt
-  io.mem_req.bits.client_xact_id := Bits(id)
+  io.mem_req.bits := Acquire(acquire_type, Cat(io.tag, req_idx).toUInt, Bits(id))
   io.mem_finish <> ackq.io.deq
 
   io.meta_read.valid := state === s_drain_rpq