riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887)

Browse Source
This commit is contained in:
Yunsup Lee
2017-07-25 00:55:55 -07:00
committed by GitHub
parent 68ed055f6d
commit c9e467a668
4 changed files with 15 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/coreplex/PeripheryBus.scala
View File

@ -7,12 +7,15 @@ import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.config.Field
case class PeripheryBusParams(
beatBytes: Int,
blockBytes: Int,
masterBuffering: BufferParams = BufferParams.default,
slaveBuffering: BufferParams = BufferParams.none,
arithmetic: Boolean = true
arithmetic: Boolean = true,
frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
) extends TLBusParams {
}