diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 374150c8..3ed5f2bd 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -35,6 +35,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
   case PLICParams => PLICParams()
   case ClintParams => ClintParams()
+  case DTSTimebase => BigInt(1000000) // 1 MHz
   // TileLink connection global parameters
   case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
   case TLCombinationalCheck => false
@@ -281,10 +282,6 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
   case NExtTopInterrupts => nExtInts
 })
 
-class WithRTCPeriod(nCycles: Int) extends Config((site, here, up) => {
-  case RTCPeriod => nCycles
-})
-
 class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
   case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n)
 })
diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 20680a7c..42352afa 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -7,12 +7,15 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
+import freechips.rocketchip.config.Field
+
 case class PeripheryBusParams(
   beatBytes: Int,
   blockBytes: Int,
   masterBuffering: BufferParams = BufferParams.default,
   slaveBuffering: BufferParams = BufferParams.none,
-  arithmetic: Boolean = true
+  arithmetic: Boolean = true,
+  frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
 ) extends TLBusParams {
 }
 
diff --git a/src/main/scala/coreplex/RTC.scala b/src/main/scala/coreplex/RTC.scala
index c83876b3..60342481 100644
--- a/src/main/scala/coreplex/RTC.scala
+++ b/src/main/scala/coreplex/RTC.scala
@@ -3,21 +3,22 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
-import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.LazyMultiIOModuleImp
+import freechips.rocketchip.diplomacy.{LazyMultiIOModuleImp, DTSTimebase}
 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
 
-/** Real-time clock is based on RTCPeriod relative to system clock.
-  */
-case object RTCPeriod extends Field[Option[Int]]
-
 trait HasRTCModuleImp extends LazyMultiIOModuleImp {
   val outer: HasPeripheryClint
-  private val internalPeriod: Option[Int] = outer.p(RTCPeriod)
-  require(internalPeriod.isDefined, "RTCPeriod is not defined")
+  private val pbusFreq = outer.p(PeripheryBusParams).frequency
+  private val rtcFreq = outer.p(DTSTimebase)
+  private val internalPeriod: BigInt = pbusFreq / rtcFreq
+
+  // check whether pbusFreq >= rtcFreq
+  require(internalPeriod > 0)
+  // check wehther the integer division is within 5% of the real division
+  require((pbusFreq - rtcFreq * internalPeriod) * 100 / pbusFreq <= 5)
 
   // Use the static period to toggle the RTC
-  val (_, int_rtc_tick) = Counter(true.B, internalPeriod.get)
+  val (_, int_rtc_tick) = Counter(true.B, internalPeriod.toInt)
 
   outer.clint.module.io.rtcTick := int_rtc_tick
 }
diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
index 8460e20e..e5ec42a6 100644
--- a/src/main/scala/system/Configs.scala
+++ b/src/main/scala/system/Configs.scala
@@ -14,8 +14,6 @@ class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) =>
   // DTS descriptive parameters
   case DTSModel => "freechips,rocketchip-unknown"
   case DTSCompat => Nil
-  case DTSTimebase => BigInt(1000000) // 1 MHz
-  case RTCPeriod => Some(1000) // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
   // External port parameters
   case IncludeJtagDTM => false
   case JtagDTMKey => new JtagDTMKeyDefault()