From c9320862aee58797cd9f144c523464a00c1b03f5 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 12 Dec 2014 12:05:41 -0800 Subject: [PATCH] add l2 dmem signal to rocc --- rocket/src/main/scala/rocc.scala | 6 ++++++ rocket/src/main/scala/tile.scala | 23 ++++++----------------- 2 files changed, 12 insertions(+), 17 deletions(-) diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index d3099043..68cef693 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -43,6 +43,7 @@ class RoCCInterface extends Bundle // These should be handled differently, eventually val imem = new UncachedTileLinkIO + val dmem = new TileLinkIO val iptw = new TLBPTWIO val dptw = new TLBPTWIO val pptw = new TLBPTWIO @@ -124,6 +125,11 @@ class AccumulatorExample extends RoCC io.imem.acquire.valid := false io.imem.grant.ready := false io.imem.finish.valid := false + io.dmem.acquire.valid := false + io.dmem.release.valid := false + io.dmem.finish.valid := false + io.dmem.probe.ready := false + io.dmem.grant.ready := false io.iptw.req.valid := false io.dptw.req.valid := false io.pptw.req.valid := false diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 04c7753d..4ad0897d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -38,10 +38,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { core.io.imem <> icache.io.cpu core.io.ptw <> ptw.io.dpath - val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts))) - val dcPortId = 0 - memArb.io.in(dcPortId) <> dcache.io.mem - memArb.io.in(1) <> icache.io.mem + val memArb = Module(new TileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts))) + io.tilelink <> memArb.io.out + memArb.io.in(0) <> dcache.io.mem + memArb.io.in(1) <> TileLinkIOWrapper(icache.io.mem) //If so specified, build an RoCC module and wire it in params(BuildRoCC) @@ -51,21 +51,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { core.io.rocc <> rocc.io dcIF.io.requestor <> rocc.io.mem dcArb.io.requestor(2) <> dcIF.io.cache - memArb.io.in(2) <> rocc.io.imem + memArb.io.in(2) <> TileLinkIOWrapper(rocc.io.imem) + memArb.io.in(3) <> rocc.io.dmem ptw.io.requestor(2) <> rocc.io.iptw ptw.io.requestor(3) <> rocc.io.dptw ptw.io.requestor(4) <> rocc.io.pptw } - - io.tilelink.acquire <> memArb.io.out.acquire - io.tilelink.grant <> memArb.io.out.grant - io.tilelink.finish <> memArb.io.out.finish - // Probes and releases routed directly to coherent dcache - io.tilelink.probe <> dcache.io.mem.probe - // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client) - io.tilelink.release.valid := dcache.io.mem.release.valid - dcache.io.mem.release.ready := io.tilelink.release.ready - io.tilelink.release.bits := dcache.io.mem.release.bits - io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts)))) - }