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tilelink2: Nodes should accept full PortParameters

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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
This commit is contained in:
Wesley W. Terpstra 2016-09-28 12:56:03 -07:00
parent f2ca2178bf
commit c85e42a303
4 changed files with 36 additions and 20 deletions
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1
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -391,6 +391,7 @@ case class TLBundleParameters(
require (isPow2(dataBits))
val addrLoBits = log2Up(dataBits/8)
val addressBits = addrHiBits + log2Ceil(dataBits/8)
def union(x: TLBundleParameters) =
TLBundleParameters(

8
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -6,13 +6,15 @@ import Chisel._
import scala.math.{min,max}
class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true)
extends TLManagerNode(beatBytes, TLManagerParameters(
extends TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(address),
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0)), // requests are handled in order
minLatency = min(concurrency, 1)) // the Queue adds at least one cycle
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1))) // the Queue adds at least one cycle
{
require (address.contiguous)

8
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -6,15 +6,17 @@ import Chisel._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0)), // requests are handled in order
minLatency = 1) // no bypass needed for this device
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = 1)) // no bypass needed for this device
// We require the address range to include an entire beat (for the write mask)
require ((address.mask & (beatBytes-1)) == beatBytes-1)

19
src/main/scala/uncore/tilelink2/TLNodes.scala
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@ -38,11 +38,22 @@ case class TLIdentityNode() extends IdentityNode(TLImp)
case class TLOutputNode() extends OutputNode(TLImp)
case class TLInputNode() extends InputNode(TLImp)
case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
case class TLClientNode(portParams: TLClientPortParameters, numPorts: Range.Inclusive = 1 to 1)
extends SourceNode(TLImp)(portParams, numPorts)
case class TLManagerNode(portParams: TLManagerPortParameters, numPorts: Range.Inclusive = 1 to 1)
extends SinkNode(TLImp)(portParams, numPorts)
case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1, minLatency: Int = 0)
extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes, minLatency), numPorts)
object TLClientNode
{
def apply(params: TLClientParameters) =
new TLClientNode(TLClientPortParameters(Seq(params)), 1 to 1)
}
object TLManagerNode
{
def apply(beatBytes: Int, params: TLManagerParameters) =
new TLManagerNode(TLManagerPortParameters(Seq(params), beatBytes, 0), 1 to 1)
}
case class TLAdapterNode(
clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,