From c85e42a3038b95f7dbf871f7096d9512fefe491d Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 28 Sep 2016 12:56:03 -0700
Subject: [PATCH] tilelink2: Nodes should accept full PortParameters

We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
---
 .../scala/uncore/tilelink2/Parameters.scala   |  1 +
 .../uncore/tilelink2/RegisterRouter.scala     | 16 ++++++++-------
 src/main/scala/uncore/tilelink2/SRAM.scala    | 20 ++++++++++---------
 src/main/scala/uncore/tilelink2/TLNodes.scala | 19 ++++++++++++++----
 4 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala
index 514e6acd..1b0b8ef4 100644
--- a/src/main/scala/uncore/tilelink2/Parameters.scala
+++ b/src/main/scala/uncore/tilelink2/Parameters.scala
@@ -391,6 +391,7 @@ case class TLBundleParameters(
   require (isPow2(dataBits))
 
   val addrLoBits = log2Up(dataBits/8)
+  val addressBits = addrHiBits + log2Ceil(dataBits/8)
 
   def union(x: TLBundleParameters) =
     TLBundleParameters(
diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
index 9732af94..7dc921b5 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
@@ -6,13 +6,15 @@ import Chisel._
 import scala.math.{min,max}
 
 class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true)
-  extends TLManagerNode(beatBytes, TLManagerParameters(
-    address            = Seq(address),
-    supportsGet        = TransferSizes(1, beatBytes),
-    supportsPutPartial = TransferSizes(1, beatBytes),
-    supportsPutFull    = TransferSizes(1, beatBytes),
-    fifoId             = Some(0)), // requests are handled in order
-    minLatency         = min(concurrency, 1)) // the Queue adds at least one cycle
+  extends TLManagerNode(TLManagerPortParameters(
+    Seq(TLManagerParameters(
+      address            = Seq(address),
+      supportsGet        = TransferSizes(1, beatBytes),
+      supportsPutPartial = TransferSizes(1, beatBytes),
+      supportsPutFull    = TransferSizes(1, beatBytes),
+      fifoId             = Some(0))), // requests are handled in order
+    beatBytes  = beatBytes,
+    minLatency = min(concurrency, 1))) // the Queue adds at least one cycle
 {
   require (address.contiguous)
 
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index 24f08540..f2191766 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -6,15 +6,17 @@ import Chisel._
 
 class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {
-  val node = TLManagerNode(beatBytes, TLManagerParameters(
-    address            = List(address),
-    regionType         = RegionType.UNCACHED,
-    executable         = executable,
-    supportsGet        = TransferSizes(1, beatBytes),
-    supportsPutPartial = TransferSizes(1, beatBytes),
-    supportsPutFull    = TransferSizes(1, beatBytes),
-    fifoId             = Some(0)), // requests are handled in order
-    minLatency         = 1) // no bypass needed for this device
+  val node = TLManagerNode(TLManagerPortParameters(
+    Seq(TLManagerParameters(
+      address            = List(address),
+      regionType         = RegionType.UNCACHED,
+      executable         = executable,
+      supportsGet        = TransferSizes(1, beatBytes),
+      supportsPutPartial = TransferSizes(1, beatBytes),
+      supportsPutFull    = TransferSizes(1, beatBytes),
+      fifoId             = Some(0))), // requests are handled in order
+    beatBytes  = beatBytes,
+    minLatency = 1)) // no bypass needed for this device
 
   // We require the address range to include an entire beat (for the write mask)
   require ((address.mask & (beatBytes-1)) == beatBytes-1)
diff --git a/src/main/scala/uncore/tilelink2/TLNodes.scala b/src/main/scala/uncore/tilelink2/TLNodes.scala
index b02c9883..f908334c 100644
--- a/src/main/scala/uncore/tilelink2/TLNodes.scala
+++ b/src/main/scala/uncore/tilelink2/TLNodes.scala
@@ -38,11 +38,22 @@ case class TLIdentityNode() extends IdentityNode(TLImp)
 case class TLOutputNode() extends OutputNode(TLImp)
 case class TLInputNode() extends InputNode(TLImp)
 
-case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
-  extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
+case class TLClientNode(portParams: TLClientPortParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SourceNode(TLImp)(portParams, numPorts)
+case class TLManagerNode(portParams: TLManagerPortParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SinkNode(TLImp)(portParams, numPorts)
 
-case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1, minLatency: Int = 0)
-  extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes, minLatency), numPorts)
+object TLClientNode
+{
+  def apply(params: TLClientParameters) =
+    new TLClientNode(TLClientPortParameters(Seq(params)), 1 to 1)
+}
+
+object TLManagerNode
+{
+  def apply(beatBytes: Int, params: TLManagerParameters) =
+    new TLManagerNode(TLManagerPortParameters(Seq(params), beatBytes, 0), 1 to 1)
+}
 
 case class TLAdapterNode(
   clientFn:        Seq[TLClientPortParameters]  => TLClientPortParameters,