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tilelink2: Nodes should accept full PortParameters

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We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
This commit is contained in:
Wesley W. Terpstra
2016-09-28 12:56:03 -07:00
parent f2ca2178bf
commit c85e42a303
4 changed files with 36 additions and 20 deletions
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20
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -6,15 +6,17 @@ import Chisel._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0)), // requests are handled in order
minLatency = 1) // no bypass needed for this device
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = 1)) // no bypass needed for this device
// We require the address range to include an entire beat (for the write mask)
require ((address.mask & (beatBytes-1)) == beatBytes-1)