riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

hookup all memory ports

Browse Source
This commit is contained in:
Yunsup Lee
2013-11-05 17:12:25 -08:00
parent 3cdfde9861
commit c810847761
2 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket

Submodule rocket updated: b246050b7d...02da61cc09

3
src/main/scala/RocketChip.scala
View File

@ -254,7 +254,8 @@ class Top extends Module {
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8, val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val hc = hwacha.HwachaConfiguration(8, 256) val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc, val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU, fpu = HAS_FPU,
rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))