From c8108477615c61e0e8e6545b38be5aecf9bbb1fa Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 5 Nov 2013 17:12:25 -0800 Subject: [PATCH] hookup all memory ports --- rocket | 2 +- src/main/scala/RocketChip.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index b246050b..02da61cc 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b246050b7de0d5610e59ec9dbdd3839759e354f9 +Subproject commit 02da61cc09e674ca9a5f9baaeac580d30cf7d693 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index f80411b2..c8444ca2 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -254,7 +254,8 @@ class Top extends Module { val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) - val hc = hwacha.HwachaConfiguration(8, 256) + val vic = ICacheConfig(128, 1) + val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU, rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))