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Add local interrupts to core (but not yet to coreplex)

This commit is contained in:
Andrew Waterman 2017-03-24 14:49:12 -07:00
parent 069858a20c
commit c7c357e716
5 changed files with 25 additions and 11 deletions

@ -1 +1 @@
Subproject commit 3e6ef13ff5cda2e65efbbf5d306cc101582ad0e5 Subproject commit 8e4ddc62db448b613ae327792e72defca4d115d4

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@ -65,7 +65,12 @@ class DCSR extends Bundle {
val prv = UInt(width = PRV.SZ) val prv = UInt(width = PRV.SZ)
} }
class MIP extends Bundle { class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero2 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
val zero1 = Bool()
val rocc = Bool() val rocc = Bool()
val meip = Bool() val meip = Bool()
val heip = Bool() val heip = Bool()
@ -119,13 +124,9 @@ object CSR
def R = UInt(5,SZ) def R = UInt(5,SZ)
val ADDRSZ = 12 val ADDRSZ = 12
def debugIntCause = { def debugIntCause = 14 // keep in sync with MIP.debug
val res = 14
require(res >= new MIP().getWidth)
res
}
def debugTriggerCause = { def debugTriggerCause = {
val res = 14 val res = debugIntCause
require(!(Causes.all contains res)) require(!(Causes.all contains res))
res res
} }
@ -211,14 +212,24 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val reg_dcsr = Reg(init=reset_dcsr) val reg_dcsr = Reg(init=reset_dcsr)
val (supported_interrupts, delegable_interrupts) = { val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(init=new MIP().fromBits(0)) val sup = Wire(new MIP)
sup.usip := false
sup.ssip := Bool(usingVM) sup.ssip := Bool(usingVM)
sup.hsip := false
sup.msip := true sup.msip := true
sup.utip := false
sup.stip := Bool(usingVM) sup.stip := Bool(usingVM)
sup.htip := false
sup.mtip := true sup.mtip := true
sup.meip := true sup.ueip := false
sup.seip := Bool(usingVM) sup.seip := Bool(usingVM)
sup.heip := false
sup.meip := true
sup.rocc := usingRoCC sup.rocc := usingRoCC
sup.zero1 := false
sup.debug := false
sup.zero2 := false
sup.lip foreach { _ := true }
val del = Wire(init=sup) val del = Wire(init=sup)
del.msip := false del.msip := false
@ -680,7 +691,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
} }
} }
reg_mip <> io.interrupts reg_mip := io.interrupts
reg_dcsr.debugint := io.interrupts.debug reg_dcsr.debugint := io.interrupts.debug
if (!usingVM) { if (!usingVM) {

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@ -17,6 +17,7 @@ case class RocketCoreParams(
useDebug: Boolean = true, useDebug: Boolean = true,
useAtomics: Boolean = true, useAtomics: Boolean = true,
useCompressed: Boolean = true, useCompressed: Boolean = true,
nLocalInterrupts: Int = 0,
nBreakpoints: Int = 1, nBreakpoints: Int = 1,
nPMPs: Int = 8, nPMPs: Int = 8,
nPerfCounters: Int = 0, nPerfCounters: Int = 0,

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@ -23,6 +23,7 @@ trait CoreParams {
val decodeWidth: Int val decodeWidth: Int
val retireWidth: Int val retireWidth: Int
val instBits: Int val instBits: Int
val nLocalInterrupts: Int
} }
trait HasCoreParameters extends HasTileParameters { trait HasCoreParameters extends HasTileParameters {

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@ -7,6 +7,7 @@ import config.Parameters
import util._ import util._
class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val debug = Bool() val debug = Bool()
val mtip = Bool() val mtip = Bool()
val msip = Bool() val msip = Bool()