From c7c357e71674fc0b5ca018d4ac040ade2cb0b5ce Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 24 Mar 2017 14:49:12 -0700
Subject: [PATCH] Add local interrupts to core (but not yet to coreplex)

---
 chisel3                              |  2 +-
 src/main/scala/rocket/CSR.scala      | 31 +++++++++++++++++++---------
 src/main/scala/rocket/Rocket.scala   |  1 +
 src/main/scala/tile/Core.scala       |  1 +
 src/main/scala/tile/Interrupts.scala |  1 +
 5 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/chisel3 b/chisel3
index 3e6ef13f..8e4ddc62 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 3e6ef13ff5cda2e65efbbf5d306cc101582ad0e5
+Subproject commit 8e4ddc62db448b613ae327792e72defca4d115d4
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index cd028a28..30cc1662 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -65,7 +65,12 @@ class DCSR extends Bundle {
   val prv = UInt(width = PRV.SZ)
 }
 
-class MIP extends Bundle {
+class MIP(implicit p: Parameters) extends CoreBundle()(p)
+    with HasRocketCoreParameters {
+  val lip = Vec(coreParams.nLocalInterrupts, Bool())
+  val zero2 = Bool()
+  val debug = Bool() // keep in sync with CSR.debugIntCause
+  val zero1 = Bool()
   val rocc = Bool()
   val meip = Bool()
   val heip = Bool()
@@ -119,13 +124,9 @@ object CSR
   def R = UInt(5,SZ)
 
   val ADDRSZ = 12
-  def debugIntCause = {
-    val res = 14
-    require(res >= new MIP().getWidth)
-    res
-  }
+  def debugIntCause = 14 // keep in sync with MIP.debug
   def debugTriggerCause = {
-    val res = 14
+    val res = debugIntCause
     require(!(Causes.all contains res))
     res
   }
@@ -211,14 +212,24 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
   val reg_dcsr = Reg(init=reset_dcsr)
 
   val (supported_interrupts, delegable_interrupts) = {
-    val sup = Wire(init=new MIP().fromBits(0))
+    val sup = Wire(new MIP)
+    sup.usip := false
     sup.ssip := Bool(usingVM)
+    sup.hsip := false
     sup.msip := true
+    sup.utip := false
     sup.stip := Bool(usingVM)
+    sup.htip := false
     sup.mtip := true
-    sup.meip := true
+    sup.ueip := false
     sup.seip := Bool(usingVM)
+    sup.heip := false
+    sup.meip := true
     sup.rocc := usingRoCC
+    sup.zero1 := false
+    sup.debug := false
+    sup.zero2 := false
+    sup.lip foreach { _ := true }
 
     val del = Wire(init=sup)
     del.msip := false
@@ -680,7 +691,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
     }
   }
 
-  reg_mip <> io.interrupts
+  reg_mip := io.interrupts
   reg_dcsr.debugint := io.interrupts.debug
 
   if (!usingVM) {
diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala
index 03857960..b3bc820c 100644
--- a/src/main/scala/rocket/Rocket.scala
+++ b/src/main/scala/rocket/Rocket.scala
@@ -17,6 +17,7 @@ case class RocketCoreParams(
   useDebug: Boolean = true,
   useAtomics: Boolean = true,
   useCompressed: Boolean = true,
+  nLocalInterrupts: Int = 0,
   nBreakpoints: Int = 1,
   nPMPs: Int = 8,
   nPerfCounters: Int = 0,
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index 3212ac77..a17544e6 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -23,6 +23,7 @@ trait CoreParams {
   val decodeWidth: Int
   val retireWidth: Int
   val instBits: Int
+  val nLocalInterrupts: Int
 }
 
 trait HasCoreParameters extends HasTileParameters {
diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala
index 2b1071e7..00a00663 100644
--- a/src/main/scala/tile/Interrupts.scala
+++ b/src/main/scala/tile/Interrupts.scala
@@ -7,6 +7,7 @@ import config.Parameters
 import util._
 
 class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
+  val lip = Vec(coreParams.nLocalInterrupts, Bool())
   val debug = Bool()
   val mtip = Bool()
   val msip = Bool()